Hardware Trojans (HTs) present significant security threats to integrated circuits. Detecting and locating HTs is crucial for mitigating these threats. Thus, this article proposes a method called HTs-GCN, which utilizes a graph convolutional network (GCN) to identify HTs. First, it extracts two novel features of gate nodes using a depth-first search strategy and topological logical analysis to enrich the feature information of circuit nodes. Second, through a message-passing mechanism, it designs a local feature aggregation method based on the GCN and a global feature fusion method based on an attention mechanism to improve the representation capability of circuit node features. Then, leveraging the concept of stochastic gradient descent and incorporating mini-batch oversampling and under-sampling techniques, it employs a dataset imbalance handling method to address the scarcity of HT nodes in circuits. These approaches significantly enhance the distinguishability between gate nodes with HTs and other gate nodes while reducing computational complexity. Experimental results indicate that HTs-GCN outperforms the recently proposed NHTD-GL method in terms of recall: it achieves approximately 7.8% points higher recall while maintaining similar accuracy. HTs-GCN demonstrates exceptional generalizability, with an average recall and accuracy of 93.0% and 100%, respectively, on infrequently used circuits in the Trust-Hub benchmark. In addition, on the TRIT-TC benchmark, HTs-GCN achieves excellent average true positive rate (TPR) and true negative rate (TNR) of 95.1% and 94.4%, respectively. Furthermore, HTs-GCN exhibits robust performance under gate modification attacks, with average TPR and TNR reaching 82.1% and 92.5%, respectively.

Hardware Trojans (HTs) pose a significant threat to the security of integrated circuits(ICs). Measuring the vulnerability of ICs to HT insertions is crucial for enhancing design security, thereby mitigating potential security risks. This paper proposes a novel vulnerability measurement method for ICs against HT insertions based on node co-activation analysis. The method first transforms the circuit structure into a graph representation, where nodes represent circuit interconnections, and edges represent circuit components, using graph learning (GL) techniques. Next, it calculates the logical probability distribution and logic flip probability for each circuit node using simulation methods. By combining an adaptive threshold filtering strategy, the method identifies suspicious nodes in the circuit using simulation methods combined with an adaptive threshold screening strategy to identify suspicious nodes in circuits. Subsequently, it computes the joint probabilities of pairs of suspicious nodes that simultaneously exhibit rare logic values based on simulation results. Finally, the vulnerability of the circuit to HT insertions is quantified by evaluating the co-activation between pairs of suspicious nodes. Experimental results demonstrate the effectiveness, efficiency, and generalization capability of the proposed method.