The solution of sparse matrix equations is essential in scientific computing. However, traditional solvers on digital computing platforms are limited by memory bottlenecks in largescale sparse matrix storage and computation. Resistive Random Access Memory (ReRAM)-based computing-in-memory (CIM) offers a promising solution to this challenge but faces constraints in achieving high solution precision and energy efficiency simultaneously in sparse matrix computations. In this work, we propose ReSMiPS, a ReRAM-accelerated sparse mixed-precision solver. ReSMiPS incorporates a novel Fast Sparse Matrix Reordering (FSMR) algorithm and introduces an In-memory float64 (IF64) data format, enabling efficient floating-point sparse matrix computation directly within the analog ReRAM array. By combining our floating-point CIM macro design with a hybrid-domain solution framework, ReSMiPS achieves precision comparable to CPU and GPU-based BiCGSTAB solvers (with errors below $10^{-15}$) on real-world workloads, while demonstrating over two orders of magnitude improvement in both computational speed and energy efficiency.

Principal component analysis (PCA) is an essential algorithm for dimensionality reduction in various data analysis tasks. Recently, PCA has gained widespread use in cloud outsourcing services due to its effectiveness and versatility. However, privacy concerns in outsourced PCA have led to the development of privacy-preserving schemes. Despite this, existing solutions face significant performance bottlenecks due to the iterative matrix computations involved in PCA, resulting in high overhead that limits their practicality. In this paper, we propose an efficient privacy-preserving outsourced PCA scheme. Specifically, we propose a secure Jacobi-EVD protocol, which improves efficiency by reducing nonlinear operations and iterations. Furthermore, by optimizing the matrix update operator in Jacobi-EVD using a hybrid protocol, we significantly reduce the communication overhead and communication rounds in iterative matrix computations. Security analysis demonstrates that our scheme preserves the privacy of data and PCA results. Performance evaluation shows our scheme significantly reduces 29.3× communication overhead compared to existing schemes.

Analog Computing-in-memory (ACIM) breaks the von Neumann bottleneck and significantly improves energy efficiency by enabling parallel matrix-vector-multiplication (MVM) operations. However, most existing ACIM accelerators are highly customized for specific precision formats, lacking the generality to support efficiently arbitrary precision in both integer (INT) and floating-point (FP) formats. In this work, we present an arbitrary precision analog computing-in-memory (ArPCIM) accelerator with unified INT/FP arithmetic to address this limitation. We introduce a CIM-friendly INT/FP arithmetic to convert FP numbers into INT numbers for efficient execution on CIM, minimizing precision loss through local pre-alignment and dynamic bit-weight slicing methods. In addition, we implement multi-level reconfigurable precision circuits, featuring both intra- and inter-processing element (PE) reconfigurability, which supports precision ranging from 1-bit to 47-bit. Experimental results show that our ArPCIM accelerator achieves up to$4.09\times $and$5.37\times $improvement in energy efficiency and area efficiency, respectively, compared with state-of-the-art arbitrary precision digital CIM. Our ArPCIM accelerator offers the flexibility to meet diverse computational needs while maintaining high energy efficiency and accuracy, paving the way for versatile CIM acceleration across various fields.