This paper presents the design and simulation of a capacitive-based Pulse Frequency Modulation (PFM) DC-DC converter with adaptive stage control, implemented in 65nm CMOS technology. Targeted for low-power energy harvesting in Wireless Sensor Networks (WSNs), the proposed architecture mitigates limitations of conventional charge pump (CP) designs, including threshold voltage losses, reversion loss, and inefficient power conversion efficiency (PCE) under varying loads. The converter integrates a high-efficiency Modified Cross-Coupled Charge Pump (MCCCP) and an adaptive stage controller using a hysteresis comparator to dynamically adjust the voltage conversion ratio (VCR) based on input voltage. Post-layout simulation results show peak PCEs of 88.23% in Doubler mode and 81.47% in Tripler mode, with consistent voltage regulation across a 0.45 V to 0.7 V input range. Compared to existing solutions, the design achieves better output power, efficiency, and adaptive performance. These attributes make the converter highly suitable for ambient energy harvesting applications in low-power Internet of Things (IoT) nodes.

This paper presents a low quiescent current outputcapacitorless low-dropout (LDO) regulator implemented in 65nm CMOS technology dedicated to the power management in Energy Harvesting Unit (EHU) applications. Most of the blocks in the proposed circuit operate in the subthreshold region in order to provide their specific outputs while consuming less current. To further reduce current consumption, a subthreshold voltage reference which can also be used to bias the error amplifier while providing a voltage reference of 500.2 mV with a TC of 55ppm/°C and a power consumption of 433.2 nW is utilized. The proposed LDO regulator uses a current-efficient adaptively biased regulation using two power transistors. The adaptive biasing circuit senses the load current and adjusts the bias point of the amplifier correspondingly. The results from the simulation demonstrate that the low dropout regulator can achieve a remarkably low quiescent current of 1.98859uA and a power consumption of 2.349134 uW under no load conditions. Additionally, the LDO regulator has a PSRR of −50.3228 dB, a good stability margin of 72.66°, and a maximum settling time of 3.437 us all under different load conditions. Moreover, the regulator can successfully maintain a regulated output voltage of 1V from a supply voltage of 1.2V, with a dropout voltage of 200 mV leading to an overall efficiency of 83.33%. Furthermore, the overall chip layout area is 0.0739 mm2.

This work presents the design of a dynamic CMOS comparator for SAR ADCs. The proposed comparator implements three improvements, namely: (1) it introduced a shared charge technique on the output terminals to reduce the delay; (2) it employed control and switch transistors on the pre-amplifier stage to reduce power consumption and (3) it replaced the PMOS tail current with NMOS to eliminate the need of an inverted clock to reduce noise. A conventional double-tail dynamic comparator is simulated alongside the proposed comparator to assess the performance of the novelty of the proposed comparator. The use of the same aspect ratio and common test bench assured the unbiased results. Results show that with 1.2GHz clock frequency and 1.2V supply voltage, the proposed comparator consumed a total average power of 886.4uW with a delay of 18.3ps, a total noise output of 0.7mVrms and an input referred noise of 7.027uVrms. While that of the conventional comparator consumed a total average power of 997.1uW with a delay of 51.93ps, a total noise output of 27.8mVrms and an input referred noise of 278uVrms.

This paper presents a novel low dropout regulator (LDO) for hearing aid applications, implemented in 65 nm CMOS technology. The LDO, designed without an output capacitor, achieves a low quiescent current of 3.09$\mu\mathbf{A}$through subthreshold operation. It features an adaptively biased regulation mechanism with two power transistors, supporting load current range up to$500\ \mu\mathbf{A}$. The Dynamic Voltage Scaling (DVS) block offers normal and low power modes, regulating output voltages to 0.7 V and 0.9 V. Simulation results show a power consumption of$3.4 \mu\mathbf{W}$, PSRR of -75 dB at 1 kHz, line and load regulation of 1.10.7 mV/V and 0.484 mV/mA, respectively, and a settling time of 1.37 to$3.6\ \mu\mathbf{s}$. The LDO maintains 0.9 V output for input voltages between 1.1 V and 1.4 V in normal mode, and 0.7 V at 1 V input in low power mode, with a dropout voltage of 100 mV and 89.89% efficiency.

An inductorless differential Low Noise Amplifier (LNA) with high linearity, designed for geofencing applications, is presented. The LNA incorporates gm-boosting, linearity optimization, and noise-cancelling stages. A complementary derivative superposition technique is used for gm-boosting, while a common-source noise-cancelling path is employed to implement the linearity enhancement stage. The design uses a differential structure for linearity optimization, addressing inherent stability issues associated with the technique. Implemented in 65nm technology, the LNA occupies a chip area of 0.037 mm2and achieves a noise figure (NF) of 3.03 dB, a peak gain of 16.78 dB, and an IIP3 linearity of 9.94 dBm, with a power consumption of 28 mW. The LNA demonstrates good stability and process variation tolerance.

This paper presents a multiband rectifier with a configurable impedance matching circuit and a low-dropout (LDO) voltage regulator for RF energy harvesting applications at 1.8GHz, 2.1GHz, and 2.4GHz frequency bands. The configurable impedance matching circuit allows the shifting between the three target impedance settings to optimize the system performance in each frequency band. The rectifier circuit is coupled with an auxiliary PMOS transistor for threshold voltage cancellation, enhancing the DC extraction efficiency of the conventional circuit. The LDO voltage regulator circuit is designed with Miller compensation to ensure stability and prevent oscillations in the control loop and a feedback capacitor to improve its transient response. Simulation results show that the overall efficiency of the proposed RF -to-DC conversion circuit is 75.4 % with power dissipation of 6.71 mW, average peak PCE of 63.7 %, and average APE of 9.4 % at the three target frequencies for a regulated DC output voltage of 1V with an output load resistance of 50k Ω. The proposed conversion circuit is implemented using 65nm CMOS technology.

This paper presents a design of a hybrid multistage differential rectifier dedicated for indoor light energy harvesters. For the first stage, a fully cross- coupled rectifier with two additional PMOS switches is used and conventional fully cross-coupled rectifiers are cascaded for the succeeding six stages. The proposed rectifier is designed using TSMC 65nm CMOS process for a smaller chip area. With an input voltage of 0.5 V operating at 10 MHz, the circuit obtained an output voltage of 2.08 V and output current of 10.4 mA. It allows improving the output current to as much as twice the value compared to that of a conventional multistage differential rectifier structure. The maximum power conversion efficiency obtained is 43.08 %. The total core chip area is 0.052 um2. All the design underwent multiple thorough verifications and simulations using Synopsys Custom Design Tool.

A triangular modulation profile using switched-capacitor scheme for spread spectrum clock generator (SSCG) is presented in this paper. The working principle consists of modulating the oscillator's constant clock frequency with a triangular signal. This will spread the energy of each harmonics into a certain frequency band, thus reducing the peak amplitude of electromagnetic interference (EMI) at harmonic frequencies. This work aims to implement triangular modulation with a constraint of 20pF total capacitor for cost efficiency. The device models of a 1um high-voltage CMOS process is applied for Hspice simulation. The modulating signal which has a frequency of 257 Hz and amplitude of 150 mVpp is used to modulate a 65 kHz oscillator. The frequency deviation is maintained to be within ± 4 kHz. Simulation shows an EMI reduction of 13.8 dB. This work is applied in the oscillator circuit of a PWM controller IC. The power consumption is 2.16mW. Theoretical analysis of traditional modulations and the proposed scheme are also formulized. The hand calculation of the modulation index using the proposed formula has only a maximum error of 3.1 percent compared to simulation.