This paper presents SP-HD, a near-sensor image classification architecture that combines stochastic computing (SC) and hyperdimensional computing (HDC) to enable energy-efficient and compact embedded intelligence. The proposed approach introduces a stochastic projection mechanism that converts input features into bitstreams, enabling bipolar multiplications to be performed with simple logic and in-memory accumulation, thereby eliminating costly multipliers and level hypervectors. A mixed-signal ReRAM-based implementation further reduces data movement by performing projection and accumulation directly within the memory fabric, while binary-weight classification minimizes circuit complexity. SP-HD achieves competitive accuracy across multiple image datasets and delivers 3μJ energy per inference with a compact 2.56mm2hardware footprint, significantly outperforming prior ReRAM compute-in-memory accelerators in both energy and area efficiency.

Hyperdimensional computing (HDC) is a promising approach for energy-efficient edge machine learning (ML), where low latency, low power, and tight memory budgets are essential. However, traditional HDC relies on symbolic binding and pseudo-random high-dimensional vectors, which require large dimensionality and heuristic updates to reach competitive accuracy, limiting deployment on edge hardware. We introduce XL-HD, a deterministic, projection-based, fully learnable HDC framework tailored for in-memory acceleration within edge computing systems. The method uses a fixed Sobol sequence to project binary inputs, extending learning beyond conventional HDC. During training, class prototypes are optimized in real-valued space and later binarized, enabling an entirely binary dot-product inference pipeline ideal for IMC hardware such as ReRAM crossbars. XL-HD achieves competitive accuracy on MNIST, UCIHAR, and ISOLET while maintaining a compact IMC-based inference engine with 0.395 mm2 area and only 0.40 μJ per single-cycle inference.

Inspired by the human brain, Hyperdimensional Computing (HDC) processes information efficiently by operating in high-dimensional space using hypervectors. While previous works focus on optimizing pregenerated hypervectors in software, this study introduces a novel on-the-fly vector generation method in hardware with $O(1)$ complexity, compared to the $O(N)$ iterative search used in conventional approaches to find the best orthogonal hypervectors. Our approach leverages Hadamard binary coefficients and unary computing to simplify encoding into addition-only operations after the generation stage in ASIC, implemented using inmemory computing. The proposed design significantly improves accuracy and computational efficiency across multiple benchmark datasets.

Content Addressable Memories (CAMs) have the ability to perform parallel searches, significantly enhancing the computational efficiency of Computing-in-Memory (CiM) architectures. CAMs can be employed in various areas, including DNA sequence analysis, IP routing, etc. Meanwhile, Ferroelectric Field Effect Transistors (FeFETs) offer a highly efficient solution for CAM implementation due to their high Ion/Ioff ratio, voltage-driven write mechanism, and non-volatility. We propose a 1FeFET analog CAM design (AFeCAM), which minimizes the area footprint compared to previous FeFET-based CAMs, making it possible to conduct searches with minimal search energy in data-intensive applications. Our AFeCAM design is ultra-compact, scalable, and uses a voltage comparator sense amplifier to detect matches and mismatches in an energy-efficient manner.

In this work, we presentODHD, an algorithm for outlier detection based on hyperdimensional computing (HDC), a non-classical learning paradigm. Along with the HDC-based algorithm, we proposeIM-ODHD, a computing-in-memory (CiM) implementation based on hardware/software (HW/SW) codesign for improved latency and energy efficiency. The training and testing phases ofODHDmay be performed with conventional CPU/GPU hardware or ourIM-ODHD, SRAM-based CiM architecture using the proposed HW/SW codesign techniques. We evaluate the performance ofODHDon six datasets from different application domains using three metrics, namely accuracy, F1 score, and ROC-AUC, and compare it with multiple baseline methods such as OCSVM, isolation forest, and autoencoder. The experimental results indicate thatODHDoutperforms all the baseline methods in terms of these three metrics on every dataset for both CPU/GPU and CiM implementations. Furthermore, we perform an extensive design space exploration to demonstrate the tradeoff between delay, energy efficiency, and performance ofODHD. We demonstrate that the HW/SW codesign implementation of the outlier detection onIM-ODHDis able to outperform the GPU-based implementation ofODHDby at least 331.5×/889× in terms of training/testing latency (and on average 14.0×/36.9× in terms of training/testing energy consumption).