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Zhao Rong

dblp:362/3661 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2023
0000-0003-0459-9770ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 50% Performance modeling and evaluation · 50%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › semiconductor device modeling
compact modeling
0.712023
Statistical Compact Modeling With Artificial Neural Networks · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023
Performance modeling and evaluation › statistical analysis
statistical modeling
0.712023
Statistical Compact Modeling With Artificial Neural Networks · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023

Methods — techniques the papers use, named apart from their topics

variational neuron selection · 0.7backward propagation of variance · 0.7artificial neural network · 0.7
YearPublicationVenuePosition
2023 Statistical Compact Modeling With Artificial Neural Networks
abstract
This work proposes a statistical modeling approach for the artificial neural network (ANN)-based compact model (CM). The method of retaining part of the network features of the nominal device and further finetuning the network parameters (variational neurons) is found to accurately reproduce the static variation. A mapping from process variation to network parameters is derived by combining the proposed variational neuron selection algorithm and the backward propagation of variance (BPV) method. In addition, a secondary classification of the selected variational neurons is applied to model the fabrication-induced correlation between n- and p-type devices. The neural network-based statistical modeling approach has been well implemented and verified on the GAA simulation data and the 16nm node foundry FinFET, which indicates its great potential in modeling emerging and advanced device technology.
Wu Dai, Zhao Rong, Baokang Peng, Lining Zhang, Runsheng Wang, Ru Huang 0001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3