For reliability-critical silicon systems, transient errors caused by cosmic rays necessitate comprehensive and efficient reliability analysis before product deployment. Fault injection (FI) serves as a cost-effective alternative to expensive irradiation experiments for evaluating system robustness. However, simulation-based FI is constrained by the performance of the underlying hardware platform, making it impractical for large-scale designs, where achieving high fault coverage can take months or even years. Furthermore, most transient errors have no impact on system functionality, and filtering out these insignificant errors in advance can significantly enhance the efficiency of reliability analysis. To address these challenges, we propose Tenpura, a fault evaluation platform designed for ultra-fast reliability analysis. In Tenpura, a transient fault scope narrowing method is introduced to narrow the FI scope via the proposed scan-based activity tracing flow, further optimizing fault analysis and improving overall efficiency. By leveraging FPGA emulation and scan chain-based fault analysis at the pre-silicon stage, Tenpura achieves high-efficiency fault reduction (88.49–96.26% across three design under tests (DUTs) including RISC-V cores and NVDLA-based AI accelerator) within one month, delivering over an order of magnitude faster fault analysis compared to SOTA methods.

Reliability-demanding devices often require numerous fault injections (FIs) for reliability analysis in the product cycle. However, software-based FI typically demonstrates extremely low efficiency due to low simulation throughput, especially for large-scale designs, while hardware-based FI presents challenges related to complexity of setup and limited scalability. Additionally, FIs often occur in intervals where errors do not affect the system’s outcome, e.g., after final read before next write, necessitating efficient pruning of non-impactful FIs. To address this, a general-purpose FI-specialized framework, Genshin, is proposed for rapid reliability analysis. On the hardware side, we provide an FI-specialized design, which works with Design Under Test (DUT) chips on PCB boards and supports FI control based on the scan chain (SC). An integrated programmable logic allows for flexible and custom FI pattern definitions. Furthermore, an architecturally correct execution (ACE) analysis generates pruned fault tables for DUTs. In Genshin, the SC logic achieves 3,802-65,388 cycles/FI across SC lengths ranging from 2,795 to 61,393 in different DUTs, while the programmable logic enables custom error patterns such as layout-aware multi-bit upset (MBU). Furthermore, the pruned fault tables achieve fault reduction rates from 45.80% to 83.21%.

In this paper, we proposed a novel probabilistic fault propagation method for circuit of the register transfer level (RTL), enabling early-stage fault injection analysis. For the proposed method, we formulate and compute the probability of fault propagating to the output of an RTL operator based on the input logic patterns. By computing the probability of operators level by level (keeping correct circuit evaluation order), we can estimate the propagation probability at destination registers for each injected fault. By the probabilistic propagation list, we can then construct a propagation graph for multi-cycle analysis to avoid lengthy fault simulations.In our experiments, the proposed method can have a speedup of 35X to 158X faster than a traditional fault injection method, while achieving an average of 94.94% accuracy in the prediction of propagation of an injected fault. Hence, the proposed method can be applied to select high-quality fault candidates and to quickly evaluate the reliability of different design choices.

Debugging is becoming increasingly important to identify functional errors of SoC caused by transient faults and to ensure system reliability. However, due to the complexity of a SoC, locating faulty signals and cycles can be challenging. Debugging flow and tool, e.g., EQED [1], applies signature blocks (MISR circuits) to capture errors and uses bounded model checking to identify transient fault candidates. In this paper, we proposed a reduction method to select essential signals for inserting and connecting signature blocks. The method identifies the propagation condition of faults and constructs a fault propagation graph (a tree of equivalent propagated faults) for the selection of essential transient faults. In our experiments of a RISC-V core, we can reduce the selected signals to about 2% on average, while maintaining more than 99% of debugging coverage.