Demo Data from EDBT 2026 / reviewers in the wild / expert
Haejin Nam
dblp:362/8747
· DBLP profile ↗
3ranked-venue papers
0as first author
3since 2021 · last 2025
0009-0007-9234-4300ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 3 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Hardware accelerators and domain-specific architectures · 41% Memory systems · 41% High-performance computing · 19% | |
| Artificial intelligence
1 paper |
Efficient and distributed learning · 100% |
Topics — the 7 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems › memory access optimization
DRAM access reduction |
0.8 | 1 | 2024 | Zero and Narrow-Width Value-Aware Compression for Quantized Convolutional Neural Networks · IEEE Trans. Computers 2024 |
Hardware accelerators and domain-specific architectures › machine learning accelerator
neural network accelerator |
0.8 | 1 | 2024 | Zero and Narrow-Width Value-Aware Compression for Quantized Convolutional Neural Networks · IEEE Trans. Computers 2024 |
Memory systems › memory access optimization
data movement reduction |
0.7 | 1 | 2023 | HARP: Hardware-Based Pseudo-Tiling for Sparse Matrix Multiplication Accelerator · MICRO 2023 |
High-performance computing › sparse linear algebra
sparse matrix multiplication |
0.7 | 1 | 2023 | HARP: Hardware-Based Pseudo-Tiling for Sparse Matrix Multiplication Accelerator · MICRO 2023 |
Hardware accelerators and domain-specific architectures
sparse matrix multiplication accelerator |
0.7 | 1 | 2023 | HARP: Hardware-Based Pseudo-Tiling for Sparse Matrix Multiplication Accelerator · MICRO 2023 |
Machine learning › Efficient and distributed learning
model compression |
0.2 | 1 | 2024 | Zero and Narrow-Width Value-Aware Compression for Quantized Convolutional Neural Networks · IEEE Trans. Computers 2024 |
Machine learning › Efficient and distributed learning › model compression
quantization |
0.2 | 1 | 2024 | Zero and Narrow-Width Value-Aware Compression for Quantized Convolutional Neural Networks · IEEE Trans. Computers 2024 |
Methods — techniques the papers use, named apart from their topics
zero run-length encoding · 1.5narrow-width value compression · 1.5software tiling · 0.7compression format · 0.7
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | C2C: A Framework for Critical Token Classification in Transformer-Based Inference SystemsabstractBecause embedding vectors in a Transformer-based model represent crucial information about input texts, attacks or errors affecting them can cause severe accuracy degradation. We observe critical tokens for the first time, that determine the overall accuracy but their embedding vectors take only a small portion of the embedding table. Therefore, we propose a framework called C2C that classifies the critical tokens to facilitate their protection in a Transformer-based inference system with a small overhead. Using BERT with GLUE datasets, critical embedding vectors take only 13.8% of the embedding table. Compromising critical embedding vectors can reduce accuracy by up to 44.8% even if other parameters are not corrupted. Myeongjae Jang, Jesung Kim, Haejin Nam, Sihyun Kim, Soontae Kim |
DATE | 3 |
| 2024 | Zero and Narrow-Width Value-Aware Compression for Quantized Convolutional Neural NetworksabstractConvolutional neural networks are normally used in systems with dedicated neural processing units for CNN-related computations. For high performance and low hardware overheads, CNN datatype quantization is applied. As an additional optimization, to further reduce DRAM accesses, compression algorithms have been used for CNN data. However, conventional zero value-aware compression algorithms suffer from a reduction in compression ratio with the latest quantized CNNs, owing to the small number of zero values. Moreover, the appropriate zero run-length code width can be changed dynamically based on the CNNs, layers, and quantization datatypes. As another compressible data value for increasing the compression ratio, the latest quantized CNNs have many narrow-width values. Because low-precision quantization reduces the data bit width, CNN data are gathered into a few discrete values and incur a biased data distribution. These discrete values become narrow-width values, and constitute a large proportion of the biased distribution. In this article, we propose an efficient compression algorithm for quantized CNNs, ENCORE, which utilizes variable zero run-length encoding and compresses narrow-width values. With the latest quantized CNNs, ENCORE shows higher compression ratios, 93.55% and 50.85% in Mobilenet v1 and Tiny YOLO v3, respectively, than conventional zero value-aware CNN data compression algorithms. Myeongjae Jang, Jinkwon Kim, Haejin Nam, Soontae Kim |
IEEE Trans. Computers | 3 |
| 2023 | HARP: Hardware-Based Pseudo-Tiling for Sparse Matrix Multiplication AcceleratorabstractGeneral sparse matrix-matrix multiplication (SpGEMM) is a memory-bound workload, due to the compression format used. To minimize data movements for input matrices, outer product accelerators have been proposed. Since these accelerators access input matrices only once and then generate numerous partial products, managing the generated partial products is the key optimization factor. To reduce the number of partial products handled, the state-of-the-art accelerator uses software to tile an input matrix. However, the software-based tiling has three limitations. First, a user manually executes the tiling software and manages the tiles. Second, generating a compression format for each tile incurs memory-intensive operations. Third, an accelerator that uses the compression format cannot skip ineffectual accesses for input matrices. Jinkwon Kim, Myeongjae Jang, Haejin Nam, Soontae Kim |
MICRO | 3 |