EDBT 2026 Demo / reviewers in the wild / expert
Zhangmai Li
dblp:362/8774
· DBLP profile ↗
2ranked-venue papers
0as first author
2since 2021 · last 2026
0009-0009-2862-8434ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Hardware accelerators and domain-specific architectures · 80% Processor architecture and microarchitecture · 20% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware accelerators and domain-specific architectures › machine learning accelerator › transformer accelerator
LLM inference accelerator |
1.0 | 1 | 2026 | Hardwired-Neuron Language Processing Units as General-Purpose Cognitive Substrates · ASPLOS (2) 2026 |
Hardware accelerators and domain-specific architectures
machine learning accelerator |
1.0 | 1 | 2026 | Hardwired-Neuron Language Processing Units as General-Purpose Cognitive Substrates · ASPLOS (2) 2026 |
Hardware accelerators and domain-specific architectures › machine learning accelerator
DNN accelerator |
0.7 | 1 | 2023 | Cambricon-U: A Systolic Random Increment Memory Architecture for Unary Computing · MICRO 2023 |
Hardware accelerators and domain-specific architectures › machine learning accelerator
neural network accelerator |
0.7 | 1 | 2023 | Cambricon-U: A Systolic Random Increment Memory Architecture for Unary Computing · MICRO 2023 |
Processor architecture and microarchitecture › computer arithmetic
unary computing |
0.7 | 1 | 2023 | Cambricon-U: A Systolic Random Increment Memory Architecture for Unary Computing · MICRO 2023 |
Processor architecture and microarchitecture
buffering |
0.2 | 1 | 2023 | Cambricon-U: A Systolic Random Increment Memory Architecture for Unary Computing · MICRO 2023 |
Methods — techniques the papers use, named apart from their topics
weight hardwiring · 1.0photomask fabrication · 1.0unary arithmetic · 0.7systolic random increment memory · 0.7
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | Hardwired-Neuron Language Processing Units as General-Purpose Cognitive SubstratesabstractThe rapid advancement of Large Language Models (LLMs) has established language as a core general-purpose cognitive substrate, driving the demand for specialized Language Processing Units (LPUs) tailored for LLM inference. To overcome the growing energy consumption of LLM inference systems, this paper proposes a Hardwired-Neurons Language Processing Unit (HNLPU), which physically hardwires LLM weight parameters into the computational fabric, achieving several orders of magnitude computational efficiency improvement by extreme specialization. However, a significant challenge still lies in the scale of modern LLMs. A straightforward hardwiring of GPT-OSS-120B would require fabricating photomask sets valued at over 6 billion dollars, rendering this straightforward solution economically impractical. Yang Liu 0466, Yongwei Zhao 0001, Yifan Hao 0001, Zifu Zheng, Weihao Kong, Zhangmai Li, Dongchen Jiang, Ruiyang Xia, Zhihong Ma, Zisheng Liu, Zhaoyong Wan, Yunqi Lu, Hongrui Guo, Zhe Wang 0017, Tianrui Ma, Mo Zou, Rui Zhang 0040, Ling Li 0001, Xing Hu 0001, Zidong Du, Zhiwei Xu 0002, Qi Guo 0001, Tianshi Chen 0002, Yunji Chen |
ASPLOS (2) | 7 |
| 2023 | Cambricon-U: A Systolic Random Increment Memory Architecture for Unary ComputingabstractUnary computing, whose arithmetics require only one logic gate, has enabled efficient DNN processing, especially on strictly power-constrained devices. However, unary computing still confronts the power efficiency bottleneck for buffering unary bitstreams. The buffering of unary bitstreams requires accumulating bits into large bitwidth binary numbers. The large bitwidth binary number needs to activate all bits per cycle in case of carry propagation. As a result, the accumulation process accounts for 32%-70% of the power budget. Hongrui Guo, Yongwei Zhao 0001, Zhangmai Li, Yifan Hao 0001, Chang Liu 0021, Xinkai Song, Xiaqing Li, Zidong Du, Rui Zhang 0040, Qi Guo 0001, Tianshi Chen 0002, Zhiwei Xu 0002 |
MICRO | 3 |