Spectrum sensing (SS) is a pivotal function in next-generation (G) multiple-input-multiple-output (MIMO) communication systems, tasked with detecting and characterizing the occupancy or availability of frequency bands within the radio spectrum. Conventional SS techniques are hindered by challenges, such as hardware complexity and the signal-to-noise ratio (SNR) wall, leading to suboptimal performance in environments with high-noise levels. Recurrent neural networks (RNNs), particularly liquid state machines (LSMs), are highly effective for developing energy-efficient accelerators, as they efficiently capture temporal dependencies in primary user frequency spectrums with a reduced number of trainable parameters. This article introduces an innovative field programmable gate array (FPGA) accelerator based on LSMs, featuring fully integrated on-chip learning capabilities for SS. Our accelerator leverages reward-based spike timing-dependent plasticity (R-STDP) to discern temporal correlations within the related frequency band. Although traditional R-STDP methods face convergence difficulties during on-chip learning, the introduced approach overcomes this challenge with a novel, hardware-efficient loss function. This mechanism which is also hardware friendly, facilitates accelerated convergence with reduction of training period of about 46.67% in SS classification for hardware implementation. Moreover, we implemented a fully asynchronous, low-latency, unsupervised triplet-based spike-time-dependent-plasticity (STDP) learning mechanism in the LSM accelerator reservoir, which improves training accuracy by about 3.88% in high-noise channels while enhancing reconfigurability. Furthermore, we investigated various encoder mechanisms to identify the most efficient encoder architecture for our LSM, leading to an accuracy increase of 6.11%. Our optimized LSM architecture achieved 1.27 times and 2.01 times the LUT and register counts, respectively, compared to the basic fixed-reservoir LSM on the Virtex-707 FPGA.

5G and beyond 5G wireless communication has revolutionized our daily lives. However, the increased bandwidth and data rate transfer in 5G present challenges, particularly in the domain of data receiving and recovery tasks. Orthogonal frequency-division multiplexing (OFDM) Symbol detection plays a pivotal role in ensuring efficient and error-free transmission in next-G communications. To ensure optimal performance and address potential bottlenecks and errors, propose a Field-Programmable Gate Array (FPGA)-based AI accelerator to accelerate symbol detection, which holds immense potential for enhancing signal recovery in MIMO systems and unlocking the full efficiency of 5G technology. To be more specific, we employ a hardware-verified Echo State Network (ESN) as the symbol detection method in the multiple-input and multiple-output (MIMO)-OFDM system. The ESN, a hardware-efficient Recurrent Neural Network, features a fixed reservoir network structure and fewer trainable parameters in the output layer. To validate our approach in real time, we construct a Software-defined Radio (SDR) platform. This platform allows us to collect datasets in real-world scenarios using antennas. Our experiment showcases a promising average bit-error rate (BER) of. 04 in the performance of our FPGA-based design under realistic conditions. We were able to achieve 3.3 times the throughput with an increase of only 21.4% LUT and 33 % FF in resource utilization for maximal processing speed design which is relatively lower in comparison with the ESN implementation for SISO systems. [1] In addition, we reduced the BRAM memory and DSP IP usage by 50% and 33.3% respectively.