With the increasing demand for on-device Artificial Intelligence (AI), various compression schemes have been proposed for DNN models to be efficiently executed on mobile devices. Although various studies have proposed compression schemes, their compatibility with mobile device memory (i.e., LPDDR) is not considered; LPDDR is prone to error as it operates at low voltage due to its strict power constraint. Currently, DRAM vendors adopt an ECC engine with SEC(136,128) code inside each LPDDR bank (i.e., IECC) for reliable operation. While IECC enhances reliability, it lowers performance due to Read-Modify-Write (RMW) and parity storage costs. Thus, for both power-efficient and reliable DNN operation in mobile environments, this paper introduces LOCo, a DNN weight compression scheme with 3-staged protection. LOCo reduces the IECC engine operation granularity from SEC(136,128) to SECDED(72,64), thus eliminating power-intensive internal reads but enhancing reliability. To mitigate the storage overhead, this paper proposes a compression scheme with protection based on the characteristics of DNN weights. Our evaluations show that LOCo provides a power reduction of 16.94%, latency reduction of 16.81%, and energy reduction of 30.81% when compared to conventional LPDDR with SEC engine, while demonstrating robustness under 17959X more bit error rate when compared to existing compression scheme.

Resistive Random-Access Memory (ReRAM)-based Processing In-Memory (PIM) Accelerator has emerged as a promising computing architecture for memory-intensive applications, such as Deep Neural Networks (DNNs). However, due to its immaturity, ReRAM devices often suffer from various reliability issues, which hinder the practicality of the PIM architecture and lead to a severe degradation in DNN accuracy. Among various reliability issues, device variation and offset current from High Resistance State (HRS) cell have been considered as major problems in a ReRAM-based PIM architecture. Due to these problems, the throughput of the ReRAM-based PIM is reduced as fewer wordlines are activated. In this paper, we propose VECOM, a novel approach that includes a variation-resilient encoding technique and an offset compensation scheme for a robust ReRAM-based PIM architecture. The first technique (i.e., VECOM encoding) is built based on the analysis of the weight pattern distribution of DNN models, along with the insight into the ReRAM's variation property. The second technique, VECOM offset compensation, tolerates offset current in PIM by mapping the conductance of each Multi-level Cell (MLC) level added with a specific offset conductance. Experimental results in various DNN models and datasets show that the proposed techniques can increase the throughput of the PIM architecture by up to 9.1 times while saving 50% of energy consumption without any software overhead. Additionally, VECOM is also found to endure low R-ratio ReRAM cell (up to 7) with a negligible accuracy drop.