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William Mitchell Hunter

dblp:364/5775 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2024
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 77% Hardware reliability and fault tolerance · 23%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › non-volatile memory
magnetic random access memory
0.812024
Design Space Exploration for Phase Transition Material-Augmented MRAMs With Separate Read-Write Paths · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024
Hardware reliability and fault tolerance › process variation
process variation tolerance
0.212024
Design Space Exploration for Phase Transition Material-Augmented MRAMs With Separate Read-Write Paths · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024

Methods — techniques the papers use, named apart from their topics

monte carlo analysis · 0.8device-circuit co-design · 0.8
YearPublicationVenuePosition
2024 Design Space Exploration for Phase Transition Material-Augmented MRAMs With Separate Read-Write Paths
abstract
This report presents a design space analysis for the phase transition material (PTM)-augmented magnetic random-access memories (MRAMs) with separate read–write paths. PTM is augmented in parallel with the magnetic tunnel junction (MTJ), improving the read performance along with providing separate read–write paths. Compared to the standard MRAM, PTM-augmented design achieves up to$1.7 \times $boost in cell tunnel magnetoresistance (CTMR),$1.2 \times $increase in read disturb margin (RDM), and${\sim }3.75 \times $increase in sense margin (SM) at the cost of${\sim }4.75 \times $more power consumption. Here, we first discuss the operating region and biasing requirements to achieve performance improvement. Then, we thoroughly explore the design space to put more options on the table for choosing the material and device structure. Finally, we perform the variation analysis where we address the performance and variation immunity tradeoffs. We demonstrate a 1000-point Monte-Carlo analysis to illustrate the effects of process variations on the performance. With lower distinguishability and read stability, the variation tolerance of the design can be improved manifold employing device-circuit co-design methodology and vice versa.
Shamiul Alam, William Mitchell Hunter, Nazmul Amin, Md. Mazharul Islam 0006, Sumeet Kumar Gupta, Ahmedullah Aziz
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2