The exponential growth in test data volume for modern Systems-on-Chip (SoCs), combined with a decreasing number of available test pins, has led to increased test time and complexity. Simultaneously, the industry’s drive for higher quality and lower Defective Parts Per Million (DPPM) necessitates continuous monitoring, testing, and repair Silicon Lifecycle Management (SLM). The advent of multi-die packaging technologies, such as 2.5D and 3D stacked integration, further exacerbates these challenges by introducing additional layers of interconnect and access constraints.Universal Chiplet Interconnect Express (UCIe) emerges as a compelling solution for delivering test content to all constituent dies at-speed, post-packaging. UCIe enables seamless test access across various lifecycle stages, including wafer sort, package test, System Level Test (SLT), and In-System Test (IST).This paper introduces a silicon-proven methodology that integrates the UCIe protocol with advanced SLM techniques to address the critical challenges of access, test, measurement and repair in complex multi-die SoC designs. Silicon results from test vehicles fabricated on TSMC N3P process with CoWoS-S packaging demonstrate complete interconnect, logic, and memory test, repair, and monitoring capabilities, validating the effectiveness and scalability of the proposed approach for next- - generation multi-die systems.

Rapid yield ramp-up and precise defect identification are crucial in advanced semiconductor development, especially as technologies reach 5nm and below. Scan-based testing, the primary Design for Testability (DFT) method, is essential, but scan chains are susceptible to defects, hindering yield learning. Traditional fault isolation, like Laser Voltage Probing, is ineffective in more advanced processes due to backside power rail constraints. Hardware solutions impact power, performance, and area (PPA), while software lacks accuracy. This paper introduces two methods to improve scan chain diagnosis: a multi-mode scan design with soft repair capability and a hybrid hardware-software approach. The multi-mode design identifies defective scan cells, aiding logic yield learning before Physical Failure Analysis (PFA), achieving a 100% predicted PFA success rate. The hybrid scalable method uses hardware for coarse diagnosis with minimal PPA impact and software for detailed analysis, leveraging existing test patterns. These approaches enhance scan chain diagnosis, supporting faster yield ramp-up and defect identification.

System-on-Wafer (SoW) technology integrates multiple chiplets onto a single wafer substrate, offering enhanced performance for high-computation applications. This paper presents an innovative 3D test access architecture designed for complex SoW systems. The proposed omnidirectional test access architecture, compliant with IEEE Std. 1838, provides a scalable, plug-and-play testing solution for comprehensive multi-directional testing. It enables efficient scan path configuration, optimizing test scheduling while reducing power consumption and minimizing timing-related impacts. A case study involving a SoW system with four chiplets arranged in a 2x2 configuration validates the architecture's feasibility and effectiveness, demonstrating its potential to enhance SoW testability and reliability.

Scan design adversely affects design performance, including speed, power, and routing congestion. Scan partitioning and reordering are required to mitigate these effects. We present an unsupervised machine learning-based method for scan partitioning to reduce the total scan wire length and make scan chains as compact as possible. For scan partitioning, we use the K-Means clustering method and reorder flops in a scan chain using the Traveling Salesman Problem (TSP) algorithm. Experimental results for three CPU designs show that significant savings in real wire length (2-3%), as well as a reduction in timing impact (27%), can be achieved with the proposed method compared to the best case obtained by a commercial EDA flow. Additionally, the optimized scan stitching also helped improve Design Rule check (DRC) violations, which aids in design closure.

A multi-die 3DIC is constructed by integrating multiple dies into a stack. These dies are interconnected via die-to-die (D2D) interconnects facilitated by I/O pads, which manage signal load and provide electrical protection to both the die and the overall system. The number of D2D interconnects is anticipated to increase significantly, rising from a few thousand today to several hundred thousand in the coming years. Consequently, ensuring the functionality and performance of 3DIC systems requires rigorous testing of not only the die logic but also the pads and interconnects at both the die and stack levels. In this paper, we explore the Design for Test (DFT) and testing challenges involved in handling various types of pads, ranging from simple to complex custom designs, within a multi-die 3DIC system. We also examine the tools and methodologies provided by Electronic Design Automation (EDA) tools to support these challenges, specifically focusing on implementations compliant with the IEEE 1838 standard.

In multi-die systems, interconnect clusters on chiplets are arranged in bump array patterns, and testing these interconnects for defects like shorts and opens is crucial for ensuring communication among different dies. Various ATPG algorithms have been developed to cover these defects. This paper introduces a fully automated EDA tool flow that utilizes the 3Dblox Open Standard to extract the physical location of interconnects and generate physical-aware test patterns. This optimized approach ensures comprehensive testing of all critical D2D interconnects, essential for a defect-free 3DIC system.

Chip-Iet based multi-die 3DIC design methodology is the paradigm shift in semiconductor manufacturing that enables scalable design integration for SysMoore era. Stacking multiple heterogeneous dies in a single stack opens chip design to a world of unexplored challenges. One such challenge is testing of the individual dies and the integrated complex stack to improve DPM. The IEEE 1838 standard defines 3DIC DFT architectures for individual dies and stack level test. In this paper we present a case study on an industrial design to leverage EDA tools and flows to implement IEEE 1838 compliant DFT architectures for full die and integrated stack.