For any unambiguous transfer of information it is critical to provide a comprehensive description of components, operations, procedures, methodology etc. defined by a technical standard. Many standards provide a descriptive language to capture and transfer information. In this paper we present a descriptive language model for Die-to-Die (D2D) interconnect test and repair, which is under development in the framework of IEEE P3405 standard. We show its capability to describe interconnect, repair scheme, and its application to existing interconnect standards like UCIe, AIB and HBM. We report the impact of various design parameters in a repair IP on the algorithm’s runtime, which extracts the repair algorithm and generates valid repair solutions from the given descriptive language in JSON format.

A multi-die 3DIC is constructed by integrating multiple dies into a stack. These dies are interconnected via die-to-die (D2D) interconnects facilitated by I/O pads, which manage signal load and provide electrical protection to both the die and the overall system. The number of D2D interconnects is anticipated to increase significantly, rising from a few thousand today to several hundred thousand in the coming years. Consequently, ensuring the functionality and performance of 3DIC systems requires rigorous testing of not only the die logic but also the pads and interconnects at both the die and stack levels. In this paper, we explore the Design for Test (DFT) and testing challenges involved in handling various types of pads, ranging from simple to complex custom designs, within a multi-die 3DIC system. We also examine the tools and methodologies provided by Electronic Design Automation (EDA) tools to support these challenges, specifically focusing on implementations compliant with the IEEE 1838 standard.

In multi-die systems, interconnect clusters on chiplets are arranged in bump array patterns, and testing these interconnects for defects like shorts and opens is crucial for ensuring communication among different dies. Various ATPG algorithms have been developed to cover these defects. This paper introduces a fully automated EDA tool flow that utilizes the 3Dblox Open Standard to extract the physical location of interconnects and generate physical-aware test patterns. This optimized approach ensures comprehensive testing of all critical D2D interconnects, essential for a defect-free 3DIC system.

Chip-Iet based multi-die 3DIC design methodology is the paradigm shift in semiconductor manufacturing that enables scalable design integration for SysMoore era. Stacking multiple heterogeneous dies in a single stack opens chip design to a world of unexplored challenges. One such challenge is testing of the individual dies and the integrated complex stack to improve DPM. The IEEE 1838 standard defines 3DIC DFT architectures for individual dies and stack level test. In this paper we present a case study on an industrial design to leverage EDA tools and flows to implement IEEE 1838 compliant DFT architectures for full die and integrated stack.