By utilizing the mapping-based pulse width modulation (MPWM), the look-up-table (LUT) based all digital transmitter (ADT) features a superb in-band signal-to-noise ratio (SNR), but its rather high random-access memory (RAM) consumption and the computation complexity hinder its further usage in applications requiring real-time reconfigurability. Our previous work leverages a Viterbi-based PWM (VbPWM) scheme to provide an iterative deduction approach, but the degraded performance and the excessive register usage make it unsuitable for real applications. By exploring the quais-periodicity inside the differenced target function, a Viterbi-based multi-bit deduction PWM (VMbPWM) is proposed in this paper, which leverages the periodic-like feature of the target function to form a multiple-bit deduction process of the 1-bit pulse sequence. Numerical simulations suggest that the proposed scheme outperforms the MPWM by a maximum of 19 dB in in-band SNR when deducing 8 bits in a single iteration, and a maximum of 10 dB increase in SNR is presented for the VMbPWM over VbPWM when the two possess the same computation complexity. After combining iterations that deduce different amounts of bits, the computation complexity of VMbPWM can be reduced to nearly 1/4 of that when deducing 8 bits in each iteration at the cost of a 5 dB SNR degradation. Accordingly, a fully pipelined ADT structure is conducted based on the VMbPWM and is implemented with the ZCU102 evaluation kit. As depicted by the implementation results, the proposed VMbPWM-based ADT reduces the RAM usage to two tiles while eliminating the register usage from 22% using VbPWM to 15% using VMbPWM. Moreover, a reduced error vector magnitude (EVM) is demonstrated for the VMbPWM, where the maximum EVM turns out to be 2.6%, 4.0%, and 4.9% under the symbol rate of 5 MBaud, 25 MBaud, and 50 MBaud using 64QAM, which is typically 0.1%-0.2% lower than the VbPWM.

Based on the concept of mapping-based pulse width modulation (MPWM), the look-up-table-based all-digital transmitter (LUT-based ADT) achieves high signal-to-noise ratio (SNR) and low error vector magnitude (EVM) by leveraging a stored mapping from the baseband complex sample to the output binary sequence, while its high RAM consumption and LUT generation complexity hinder its further usage. Toward a RAM-free and traversal-free ADT based on MPWM, in this paper, we model the MPWM process as an optimization problem and correspondingly construct a Viterbi-based PWM (VbPWM) modulator scheme, featuring real-time deduction of the 1-bit sequence from the input complex sample and a traversal-free computation process. Fixed points simulations suggest that the deduced local optimum demonstrates a 10 dB SNR loss compared with the global optimum of MPWM, while this loss can be further eased by 2-3 dB after introducing a simplified simulated annealing algorithm. Additionally, a fully serial and pipelined implementation structure is proposed to unfold the iterations into cascading iteration units, thereby achieving run-time reconfigurable carrier frequencies and minimizing block read-only memory (BRAM) usage. EVMs of the proposed ADT with carrier frequencies ranging from 0.6 GHz and 7.6 GHz under different symbol rates are measured with ZCU102, presenting an increasing trend associated with carrier frequency and symbol rates. Consequently, compared with the original MPWM, a 1% loss of EVM is revealed under 5 MBaud of symbol rate for all measured frequencies. The maximum EVM under 5 MBaud is measured as 3.5%, while the maximum for 25 MBaud and 50 MBaud is 5% and 5.8%, respectively. The RAM usage is then minimized to a single 36K tile and the traversal of MPWM is removed.

The bandwidth of the frequency-modulated continuous wave (FMCW) system is largely increased with the progress in high-speed technology to achieve high accuracy ranging. In situations where bandwidth is restricted, the range estimation algorithm is still worth concern. By breaking down the range estimation of the FMCW system into single-tone frequency estimation, in this paper we propose a Phase-Difference-based Single-Tone estimation (PDb-STE) algorithm consisting of two fast Fourier transform (FFT) units and an interpolator. Spectra obtained from the FFT units are utilized to form a phase difference, which is used for the FFT enhancement. Frequency, phase and amplitude estimations are carried out based on the corrected phase difference. Theoretical proof of the proposed algorithm is given under the rectangular window and further applied with Hann, Hanning, Blackman and Kaiser windows during simulation. The results show that for Kaiser window the expanded main lobe brings less systematic error for both complex signal estimation and in-phase part estimation. Simulation of FMCW system is performed based on proposed algorithm. By setting iteration chirp-Z transform (CZT) as the comparison, the proposed algorithm outperforms the CZT by 1 dB under rectangular and Kaiser window with the main lobe control factor β ≤ 2.5. The performance worsens as the β grows, which is due to the increased noise disruption to the wide main lobe. Hardware verification is carried out to show the feasibility of the algorithm and obtain results with all root mean square error(RMSE) below 0.02 m.