The combined use of algorithms for approximate discrete cosine transform (DCT) with approximate computing is examined toward area-efficient field programmable gate array (FPGA) hardware architectures. The performance of previously reported, multiplierless approximate DCT transforms are explored in the presence of non-exact hardware adders which provide better utilisation of FPGA resources in terms of look-up-tables (LUTs). In the context of 2D image compression, provided examples are demonstrating a 20% LUT reduction in FPGA utilization compared to accurate adders, with a corresponding image quality degradation of 0.6 dB in terms of PSNR. The potential benefit of such area-efficient FPGA hardware designs is explored on 3D (video compression), 4D (static light field compression), and 5D (light field video compression) cases where significant FPGA resource savings are obtained at the cost of marginal degradation of output quality.

We propose a minimax design method for multi-dimensional (M-D) interpolated finite-support impulse response (IFIR) filters. As a result of the cascade structure of an MD IFIR filter, the optimization problem of the minimax design is nonconvex. In order to solve this nonconvex optimization problem, we employ a convex-concave procedure, where each iteration solves a convex constrained optimization problem. We present experimental results to confirm the effectiveness and the superior performance of the proposed method compared to previously proposed minimax designs of M-D IFIR filters. Furthermore, we present an implementation of M-D IFIR filter on the Xilinx Kintex UltraScale KCU105 field-programmable gate array, where a quantization error of −60.59 dB is achieved with the coefficient word length of 24 bits.

Chromatic derivatives (CDs) and associated chromatic approximations (CAs) provide a numerically robust and powerful framework for digital processing of continuous-time/space signals, using not only the discrete signal amplitudes, but also higher order derivatives. Acquisition of CDs has so far been limited to software implementations. This paper presents field-programmable gate array (FPGA)-based digital hardware architectures suitable for the real-time acquisition of CDs, thus enabling CDs to be used for practical signal processing algorithm development in embedded systems. With 24 bits of fixed-point precision, the proposed hardware architectures provide approximate 116 dB accuracy in the frequency responses of FIR filters capturing the CDs, and 76.85 dB and 75.09 dB accuracy in signal reconstruction with synthetic and real audio signals using CDs up to order 28 degrees. The designs have been verified on an AMD Kintex UltraScale KCU105 FGPA device using bit-true cycle-accurate hardware co-simulation.