This paper presents a comparative study of two maximum power point tracking (MPPT) algorithms-Enhanced Perturb and Observe (P&O) and Fractional Open-Circuit Voltage (FOCV)-targeted for indoor photovoltaic (PV) energy harvesting applications. Both designs were implemented using the 65 nm CMOS process in Cadence Virtuoso and integrated with a boost converter to ensure efficient energy transfer under low-light conditions. The evaluation focuses on key performance metrics including output voltage, settling time, ripple voltage, boost accuracy, and power consumption. Simulation results show that both algorithms achieve comparable performance in terms of output voltage stability and ripple control, with post-simulation ripple voltages of 0.622 % for Enhanced$\mathrm{P} \& \mathrm{O}$and 0.641 % for FOCV, and boost accuracies above 99 % for both. However, Enhanced P&O clearly outperforms FOCV in terms of settling time, achieving$370 \mu ~\mathrm{s}$compared to$810 \mu ~\mathrm{s}$, making it more suitable for applications requiring dynamic adaptation and fasttracking response. On the other hand, while FOCV demonstrates slightly higher power consumption and slower response, it offers lower circuit complexity and simplified control implementation due to the absence of current sensing and a feedback loop. These trade-offs highlight the strengths of each technique depending on application-specific constraints.

This paper presents a low quiescent current outputcapacitorless low-dropout (LDO) regulator implemented in 65nm CMOS technology dedicated to the power management in Energy Harvesting Unit (EHU) applications. Most of the blocks in the proposed circuit operate in the subthreshold region in order to provide their specific outputs while consuming less current. To further reduce current consumption, a subthreshold voltage reference which can also be used to bias the error amplifier while providing a voltage reference of 500.2 mV with a TC of 55ppm/°C and a power consumption of 433.2 nW is utilized. The proposed LDO regulator uses a current-efficient adaptively biased regulation using two power transistors. The adaptive biasing circuit senses the load current and adjusts the bias point of the amplifier correspondingly. The results from the simulation demonstrate that the low dropout regulator can achieve a remarkably low quiescent current of 1.98859uA and a power consumption of 2.349134 uW under no load conditions. Additionally, the LDO regulator has a PSRR of −50.3228 dB, a good stability margin of 72.66°, and a maximum settling time of 3.437 us all under different load conditions. Moreover, the regulator can successfully maintain a regulated output voltage of 1V from a supply voltage of 1.2V, with a dropout voltage of 200 mV leading to an overall efficiency of 83.33%. Furthermore, the overall chip layout area is 0.0739 mm2.

This study introduces a configurable Maximum Power Point Tracker (MPPT) designed for energy harvesting systems, focusing on optimizing output power from ambient light using photovoltaic (PV) cells and heat gradient from thermoelectric generators (TEG). Utilizing the Fractional Open Circuit Voltage (FOCV) algorithm, the configurable MPPT system achieves a tracking efficiency that exceeds 90 percent for PV cells and over 70 percent for TEG. Notably, it demonstrates excellent performance in tracking the Vmpp for PV cells for 0.8V to 1.2V input voltage. Also, it effectively tracks the Vmpp for TEG systems, consistently maintaining a stable output response for input voltages below 0.6V relative to Voc. The power consumption of the MPPT system remained relatively low, measuring$246.4\text{uW}$when a PV source is utilized and$217.5\text{uW}$when a TEG source is employed, indicating efficient operation.

This paper presents a novel low dropout regulator (LDO) for hearing aid applications, implemented in 65 nm CMOS technology. The LDO, designed without an output capacitor, achieves a low quiescent current of 3.09$\mu\mathbf{A}$through subthreshold operation. It features an adaptively biased regulation mechanism with two power transistors, supporting load current range up to$500\ \mu\mathbf{A}$. The Dynamic Voltage Scaling (DVS) block offers normal and low power modes, regulating output voltages to 0.7 V and 0.9 V. Simulation results show a power consumption of$3.4 \mu\mathbf{W}$, PSRR of -75 dB at 1 kHz, line and load regulation of 1.10.7 mV/V and 0.484 mV/mA, respectively, and a settling time of 1.37 to$3.6\ \mu\mathbf{s}$. The LDO maintains 0.9 V output for input voltages between 1.1 V and 1.4 V in normal mode, and 0.7 V at 1 V input in low power mode, with a dropout voltage of 100 mV and 89.89% efficiency.

Boost converters have been widely adopted in battery-powered technologies due to their compact size, afford-ability, and ability to generate a higher output voltage than the input voltage. Regulating the output voltage is crucial for these converters in portable devices, as these devices operate across a wide range of current loads, potentially affecting output voltage stability. Feedback loops in boost converters can effectively address this regulation issue. A key component in these feedback loops is the clock generator, which manages the switching activities of the boost converter. It controls the inductor's charging and discharging phases to produce the boosted output voltage. This paper introduces a non-overlapping synthetic clock generator for boost converters, designed to maintain an almost constant switching frequency for stable output voltage regulation across a wide load current range. This system is implemented using the TSMC 65nm CMOS technology process.

This paper presents a multiband rectifier with a configurable impedance matching circuit and a low-dropout (LDO) voltage regulator for RF energy harvesting applications at 1.8GHz, 2.1GHz, and 2.4GHz frequency bands. The configurable impedance matching circuit allows the shifting between the three target impedance settings to optimize the system performance in each frequency band. The rectifier circuit is coupled with an auxiliary PMOS transistor for threshold voltage cancellation, enhancing the DC extraction efficiency of the conventional circuit. The LDO voltage regulator circuit is designed with Miller compensation to ensure stability and prevent oscillations in the control loop and a feedback capacitor to improve its transient response. Simulation results show that the overall efficiency of the proposed RF -to-DC conversion circuit is 75.4 % with power dissipation of 6.71 mW, average peak PCE of 63.7 %, and average APE of 9.4 % at the three target frequencies for a regulated DC output voltage of 1V with an output load resistance of 50k Ω. The proposed conversion circuit is implemented using 65nm CMOS technology.