EDBT 2026 Demo / reviewers in the wild / expert
Jun Yan Lee
dblp:365/7216
· DBLP profile ↗
2ranked-venue papers
1as first author
2since 2021 · last 2025
0009-0002-2375-5572ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-author · 2 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Hardware accelerators and domain-specific architectures · 42% Memory systems · 31% Emerging computing paradigms · 21% |
Topics — the 11 heaviest of 11, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware accelerators and domain-specific architectures › machine learning accelerator
inference accelerator |
0.9 | 1 | 2025 | PolymorPIC: Embedding Polymorphic Processing-in-Cache in RISC-V based Processor for Full-stack Efficient AI Inference · MICRO 2025 |
Hardware accelerators and domain-specific architectures
machine learning accelerator |
0.9 | 1 | 2025 | PolymorPIC: Embedding Polymorphic Processing-in-Cache in RISC-V based Processor for Full-stack Efficient AI Inference · MICRO 2025 |
Hardware accelerators and domain-specific architectures › machine learning accelerator
neural network accelerator |
0.9 | 1 | 2025 | BiNeuroRAM: Energy-Efficient ReRAM-Based PIM for Accurate Bipolar Spiking Neural Network Acceleration · DAC 2025 |
Emerging computing paradigms
neuromorphic computing |
0.9 | 1 | 2025 | BiNeuroRAM: Energy-Efficient ReRAM-Based PIM for Accurate Bipolar Spiking Neural Network Acceleration · DAC 2025 |
Memory systems › processing-in-memory
processing-in-cache |
0.9 | 1 | 2025 | PolymorPIC: Embedding Polymorphic Processing-in-Cache in RISC-V based Processor for Full-stack Efficient AI Inference · MICRO 2025 |
Memory systems
processing-in-memory |
0.9 | 1 | 2025 | BiNeuroRAM: Energy-Efficient ReRAM-Based PIM for Accurate Bipolar Spiking Neural Network Acceleration · DAC 2025 |
Memory systems › processing-in-memory
ReRAM-based processing-in-memory |
0.9 | 1 | 2025 | BiNeuroRAM: Energy-Efficient ReRAM-Based PIM for Accurate Bipolar Spiking Neural Network Acceleration · DAC 2025 |
Emerging computing paradigms › neuromorphic computing
spiking neural network |
0.9 | 1 | 2025 | BiNeuroRAM: Energy-Efficient ReRAM-Based PIM for Accurate Bipolar Spiking Neural Network Acceleration · DAC 2025 |
Hardware accelerators and domain-specific architectures › machine learning accelerator › neural network accelerator
spiking neural network accelerator |
0.9 | 1 | 2025 | BiNeuroRAM: Energy-Efficient ReRAM-Based PIM for Accurate Bipolar Spiking Neural Network Acceleration · DAC 2025 |
Energy-efficient computing › energy-efficient architecture
energy-efficient accelerator |
0.3 | 1 | 2025 | BiNeuroRAM: Energy-Efficient ReRAM-Based PIM for Accurate Bipolar Spiking Neural Network Acceleration · DAC 2025 |
Processor architecture and microarchitecture › microprocessor design
RISC-V processor |
0.3 | 1 | 2025 | PolymorPIC: Embedding Polymorphic Processing-in-Cache in RISC-V based Processor for Full-stack Efficient AI Inference · MICRO 2025 |
Methods — techniques the papers use, named apart from their topics
voltage sense amplifier · 0.9asynchronous microarchitecture · 0.9ReRAM · 0.9
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | BiNeuroRAM: Energy-Efficient ReRAM-Based PIM for Accurate Bipolar Spiking Neural Network AccelerationabstractReRAM is a promising non-volatile memory for neuromor-phic accelerators, yet it faces challenges such as high sensing power and accuracy degradation. This work proposes BiNeuroRAM, a novel spiking neural network (SNN) accelerator leveraging ReRAM-based processing-in-memory (PIM), with three key contributions: (1) It is the first to support higher-accuracy spike-tracing bipolar-integrate-and-fire (ST-BIF) neurons, achieving 80.9% accuracy on ImageNet, 8.4% higher than the previous state-of-the-art; (2) It introduces a low-power voltage sense amplifier (LPVSA) that reduces ReRAM read power by 14.7~58.2×, enhancing energy efficiency; (3) It employs an asynchronous micro-architecture that fully exploits the event-driven nature of SNNs. Experimental results show that BiNeuroRAM improves throughput density and energy efficiency by 2.08× and 2.09× on ImageNet with ResNet-18, compared to traditional integrate-and-fire (IF) neuron-based SNN accelerators. Jun Yan Lee, Chen Nie, Kang You, Yueyang Jia, Zhezhi He |
DAC | 1 |
| 2025 | PolymorPIC: Embedding Polymorphic Processing-in-Cache in RISC-V based Processor for Full-stack Efficient AI Inference
Ziling Wei, Jun Yan Lee, Chen Nie, Kang You, Zhezhi He |
MICRO | 3 |