Demo Data from EDBT 2026 / reviewers in the wild / expert
Huangxu Chen
dblp:366/6984
· DBLP profile ↗
2ranked-venue papers
1as first author
2since 2021 · last 2025
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-author · 2 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware accelerators and domain-specific architectures · 100% | |
| Artificial intelligence
1 paper |
Efficient and distributed learning · 100% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware accelerators and domain-specific architectures › machine learning accelerator › transformer accelerator
large language model accelerator |
0.9 | 1 | 2025 | An Algorithm-Hardware Co-design Based on Revised Microscaling Format Quantization for Accelerating Large Language Models · DAC 2025 |
Hardware accelerators and domain-specific architectures
machine learning accelerator |
0.9 | 1 | 2025 | An Algorithm-Hardware Co-design Based on Revised Microscaling Format Quantization for Accelerating Large Language Models · DAC 2025 |
Hardware accelerators and domain-specific architectures
quantization |
0.9 | 1 | 2025 | An Algorithm-Hardware Co-design Based on Revised Microscaling Format Quantization for Accelerating Large Language Models · DAC 2025 |
Machine learning › Efficient and distributed learning › model compression › quantization
low-bit quantization |
0.3 | 1 | 2025 | An Algorithm-Hardware Co-design Based on Revised Microscaling Format Quantization for Accelerating Large Language Models · DAC 2025 |
Machine learning › Efficient and distributed learning
model compression |
0.3 | 1 | 2025 | An Algorithm-Hardware Co-design Based on Revised Microscaling Format Quantization for Accelerating Large Language Models · DAC 2025 |
Methods — techniques the papers use, named apart from their topics
quantization · 1.7algorithm-hardware co-design · 1.7
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | An Algorithm-Hardware Co-design Based on Revised Microscaling Format Quantization for Accelerating Large Language ModelsabstractThe narrow-bit-width data format is crucial for reducing the computation and storage costs of modern deep learning applications, particularly in large language models (LLMs) based applications. Microscaling (MX) format has been proven as a drop-in replacement for the baseline FP32 in existing inference frameworks, with low user friction. However, deploying such a new format into existing hardware systems is still challenging, and the dominant solution for LLM inference at low precision is still low-bit quantization. This particularly limits the strategic applications of such LLMs in real deployment on a large scale. In this work, we propose an algorithm-hardware co-design that adopts a two-level $Revised MX Format Quantization$ (RMFQ) and a $Revised MX Format Accelerator$ (RMFA) architecture design. RMFQ proposes the $revised M X(R M X)$ format and provides a novel quantization framework with innovative group direction. Also, RMFA provides an RMX adaptive hardware architecture and an RMX encoding scheme. As a result, RMFQ pushes the limit of 4-bit and 6-bit quantization to a new state-of-the-art, and RMFA surpasses the existing outlier-aware accelerator such as OliVe, achieving a $1.28 \times$ speedup and a $1.31 \times$ energy reduction. Yingbo Hao, Huangxu Chen |
DAC | 2 |
| 2025 | OA-LAMA: An Outlier-Adaptive LLM Inference Accelerator with Memory-Aligned Mixed-Precision Group QuantizationabstractLarge language models (LLMs) face significant deployment challenges due to their substantial memory and computational demands. While low-precision quantization offers a promising solution, the presence of activation outliers severely degrades model accuracy. Existing approaches either compromise hardware efficiency through misaligned memory access or sacrifice quantization granularity through rigid bit-width allocation, particularly when handling non-uniform tensor distributions across and within layers. This paper presents a hardware-software co-designed framework resulting in an outlier-adaptive LLM inference accelerator with memory-aligned mixed-precision group quantization, named OA-LAMA. The framework comprises three key innovations: First, an outlier-adaptive memory-aligned mixed-precision group (OAMAG) format with a novel outlier reordering technique is proposed to preserve accuracy while maintaining DRAM-aligned memory access. Second, a distribution-aware group allocation strategy is proposed to address inter-layer outlier ratio variance. Finally, we design the OA-LAMA hardware architecture with a three-level accumulation architecture and timing-balanced processing elements to support the OAMAG format efficiently. Evaluations demonstrate that OA-LAMA achieves better accuracy than state-of-the-art 4-bit quantization methods while delivering 1.21–3.09× performance improvement and 1.35–2.47× energy efficiency gains over leading LLM accelerators. OA-LAMA establishes new Pareto frontiers in accuracy-efficiency co-optimization for LLM inference. OA-LAMA is open-sourced at https://github.com/CLab-HKUST-GZ/ICCAD25_OA-LAMA.git. Huangxu Chen, Yingbo Hao, Yi Zou 0001 |
ICCAD | 1 |