Silicon Dangling Bond (SiDB) logic is a promising technology for energy-efficient computation, supported by significant advancements in manufacturing and design automation. However, physical simulation, essential for accurately predicting the behavior of SiDB logic prior to costly manufacturing, lags behind these developments. In particular, exact physical simulation, which scales exponentially with base 3, remains infeasible for larger SiDB assemblies, limiting its utility to small structures such as single gates. This computational bottleneck slows progress in SiDB technology and hinders the establishment of reliable ground truths for heuristic approaches. To address the challenge, this work presents a novel methodology for exact SiDB simulation that restructures the exponential search space according to a hierarchical clustering. The hierarchy structure enables a systematic pruning of the search space at its different levels: it provides an ordering of interactions between clusters of SiDBs to facilitate efficacious exploitation of dynamically-inferred problem-specific constraints-like solving a Sudoku. Experimental results demonstrate that the effective exponential base can be lowered to approximately 1.3, enabling, for the first time, the exact physical simulation of entire multi-gate SiDB circuits in minutes that would take the state of the art millions of years to compute. This breakthrough establishes a robust ground truth for SiDB logic validation, marking a pivotal step toward scalable, energy-efficient, and atomic-scale computing.

In recent years,Silicon Dangling Bond(SiDB) logic has emerged as a promising beyond-CMOS technology due to its integration density and operating frequency. This advancement is driving the development of comprehensive design automation workflows, including physical simulators and gate design tools. Unlike conventional circuit technology, where logic is implemented through transistors, SiDB logic utilizes quantum dots with variable charge states. By strategically arranging these dots, standard logic functions like OR, AND, NAND, etc. can be implemented, which are usually provided asStandard Cellsin design processes. However, finding such arrangements that implement a given Boolean function is a tremendously complex task that involves considering numerous candidates and verifying them through computationally expensive physical simulation. Hence, the automatic obtainment of SiDB logic layouts is thus far limited to simple 2-input functions only— which already require substantial computation resources. In contrast, conventional physical design algorithms for VLSI have long transitioned from single-gate considerations to multi-input standard cells. To address this challenge, this paper proposesQuickCell: A fast algorithm for automatic standard cell design for SiDB logic that uses dedicated search space pruning techniques. In an extensive experimental evaluation, it is demonstrated that combining these pruning techniques yields 1) a drastic reduction of the search space amounting to up to six orders of magnitude, 2) a corresponding decrease of the runtime by up to a factor of 91, 3) the capability to handle more complex functionality, as, e. g., utilized in standard cells, for the first time, significantly narrowing the gap between SiDB logic and conventional CMOS design paradigms, and 4) a significant speedup compared to physical simulation (up to a factor of 10 000), with near independence from the number of I/O pins when determining the non-operationality of a given layout. This efficiency makes these techniques—and by extensionQuickCell—a powerful enabler for the design of complex standard cells.

In recent years, Silicon Dangling Bond (SiDB) logic has emerged as a promising beyond-CMOS technology. Unlike conventional circuit technology, where logic is realized through transistors, SiDB logic utilizes quantum dots with variable charge states. By strategically arranging these dots, logic functions can be constructed. However, determining such arrangements is a tremendously complex task. Because of that, the automatic obtainment of SiDB logic implementations is inefficient. To address this challenge, we propose an idea to speed up the design process by utilizing dedicated search space pruning strategies. Initial results show that the combined pruning techniques yield 1) a drastic reduction of the search space, and 2) a corresponding reduction in runtime by up to a factor of 33.

As traditional transistor scaling reaches its physical and economic limits, Silicon Dangling Bond (SiDB) logic is emerging as a promising post-CMOS technology for atomic-scale computation. However, despite mitigation efforts, atomic defects persist on the hydrogen-passivated silicon surface and remain challenging to eliminate. Since SiDB logic is highly sensitive to these charged atomic defects, efficient defect robustness simulation is essential for reliable SiDB logic design and successful operation. Existing simulation methods, however, are inefficient, limiting their practical applicability. To address this shortcoming, we present QuickTrace, an efficient algorithm to simulate the defect robustness of SiDB logic. QuickTrace uses contour tracing to identify the boundary in the simulation area between operational and non-operational states caused by defect positions, allowing defect robustness to be simulated with significantly fewer simulator calls. Experimental evaluations show that QuickTrace precisely and accurately computes defect robustness while avoiding the need to consider 88% of potential defect positions in simulations—and thus reducing runtime by the same percentage—compared to the state-of-the-art approach. This enables efficient and scalable defect robustness simulation of SiDB logic for the first time, contributing to the advancement of SiDB technology as a promising post-CMOS technology.

This demonstration presents the Operational Domain Explorer, a PyQt6-based application designed for computationally efficient resilience analysis of Silicon Dangling Bond (SiDB) logic layouts. Leveraging novel algorithms, the tool significantly reduces the simulation load required for operational domain evaluations, supporting real-time, multi-dimensional visualizations and advancing SiDB layout reliability.

The Silicon Dangling Bond (SiDB) logic platform, an emerging computational beyond-CMOS nanotechnology, is a promising competitor due to its ability to achieve integration density and clock speed values that are several orders of magnitude higher compared to current CMOS fabrication nodes. However, the exact physical simulation of SiDB layouts, which is an essential component of any design validation workflow, is computationally expensive. In this paper, we propose a novel algorithm called QuickExact, which aims to be both, efficient and exact. To this end, we are introducing three techniques, namely 1) Physically-informed Search Space Pruning, 2) Partial Solution Caching, and 3) Effective State Enumeration. Extensive experimental evaluations confirm that, compared to the state-of-the-art algorithm, the resulting approach leads to a paramount runtime advantage of more than a factor of 5000 on randomly generated layouts and more than a factor of 2000 on an established gate library.