This article presents a 24-MHz fast startup crystal oscillator (XO) with a phase-interpolator-assisted synchronized injection technique. The technique ensures phase consistency between the injection source and the crystal resonance, even with a 2% injection-$\Delta F$, enhancing the robustness of the startup under different PVT conditions. Additionally, we propose a differential peak detection technique to detect the phase error incurred by$\Delta F$. Such a peak detection technique shortens the auxiliary non-injection period during startup to merely four cycles, thereby maximizing the injection percentage to 97.4% and enhancing the startup’s efficacy. Fabricated in the 40-nm CMOS process, the XO achieves a 6.9-$\mu $s startup time (166 cycles) with a startup energy of 4.8 nJ under a 1-V$V_{\text {DD}}$. Furthermore, the startup time varies by ±4.4%, ±3.6%, and ±5.1% (worst case) over$\Delta F$(0.25% to 2%), temperature (−40 to$85~^{\circ }$C), and$V_{DD}$(0.95 to 1.05 V) variations, respectively. The XO’s phase noise in the steady-state is −137.8dBc/Hz at the 1-kHz offset, with a power consumption of$63~\mu $W.

This article presents a systematic design methodology for multi-input piezoelectric energy harvesting (PEH) using collaborative-flip synchronized switch harvesting on capacitors (CF-SSHCs). We address a fundamental scaling limitation: conventional synchronized switch harvesting on capacitor (SSHC) efficiency degrades as the number of parallel transducers increases due to rising equivalent capacitance. Starting from the theoretical foundations of a two-transducer single-stage topology, we develop closed-form expressions for the voltage flipping factor and power extraction that reveal a 7.4% maximum power improvement over conventional SSHC. Extending to multistage architectures, results show that an 8-stage configuration achieves 32.2% power enhancement through 33 collaborative-flipping phases. For generalized$M$-input$N$-stage systems, the derived analytical framework demonstrates that the maximum output power improvement ratio (MOPIR) scales from 3.8 to 9 as transducer count increases from 1 to 60 in an 8-stage implementation. We formulate an optimization algorithm for automated parameter selection and provide closed-form design equations considering practical issues, including phase asynchrony and capacitance mismatch. This work establishes a complete theoretical framework enabling systematic design of multitransducer energy harvesting interfaces rather than empirical topology exploration.

Insulated gate bipolar transistors (IGBTs) are the key component in power electronics, and the intricate relationship between their performance and structural parameters poses a formidable challenge in the design process. This article proposes an automatic optimal design method for IGBT structural parameters to leverage the pretrained machine learning (ML) model to efficiently predict the initial IGBT device’s performance, followed by utilizing the differential evolution (DE) algorithm to automatically adjust structural parameters based on the disparity between predicted and expected device performance until the expected performance is achieved. The method is validated in the design of punch-through IGBTs (PT-IGBTs) and trench gate field-stop IGBTs (FS-IGBTs), and the performance of technology computer-aided design (TCAD) simulation of the designed device is similar to the target performance. In particular, the simulation results of the designed FS-IGBT are highly fitted to the datasheet of the commercial device, which verifies the generalizability and effectiveness of the method. In addition, comparative analyses with various algorithms show DE provides the fastest optimization and extraordinary robustness under the exact specifications. Crucially, the proposed design scheme aligns with semiconductor physics. The method simplifies IGBT design without the need for manual tuning and TCAD tool simulation.