In advanced technology nodes, Current Source Models (CSMs) are widely adopted due to their high accuracy. However, IR-drop–induced supply voltage fluctuations increase the computational burden of CSM-based timing analysis. Existing machine-learning (ML) approaches accelerate CSM evaluation by assuming fixed receiver capacitance along the path, which contradicts the variable-load dependency inherent to CSM formulation. In this work, we propose GoG-Predict, a fast and accurate IR-aware path waveform prediction framework. GoG-Predict employs a Graph-of-Graphs (GoG) Neural Network to model the structured interactions among driver cells, load nets, and receiver cells. In addition, a Feature-wise Linear Modulation (FiLM) mechanism is incorporated to account for the impact of IR drop on output waveform. We evaluate GoG-Predict on open-source designs using a commercial 12nm technology. Experimental results show an average waveform error of 2.03% and a 1426 × runtime speedup over HSPICE, while achieving 1.63 × higher accuracy compared with state-of-the-art ML-based prediction methods.

As process nodes shrink, intensified IR drop and electromigration (EM) issues, driven by the power delivery network (PDN), affect reliability and further compress the routability of the entire design. Since physical design is time-consuming, effectively predicting and optimizing PDN during the power planning stage is crucial. This effort is complicated by complex interactions between multiple parameters and the challenges associated with nonconvex optimization. To overcome these limitations, we propose a learning-driven hierarchical particle swarm optimization framework for PDN, integrated with a residual TransUNet-based prediction model for post-placement congestion, EM, and IR drop prediction. In addition, we introduce the gate network for loss fusion, which excels in balancing output predictions and enhancing the accuracy of critical tasks. Analogous to hyperparameter optimization in deep learning, we can utilize GPU parallelization to search for the global optimum of the PDN structure efficiently. In circuits at the 22nmand 16nmtechnology nodes, with cell counts ranging from 560 to nearly 200, 000, our method achieves reductions in mean and maximum congestion by 15% and 49%, respectively, compared to state-of-the-art methods. In addition, it achieves an overall optimization time of around 22 seconds.

As semiconductor processes advance, the power delivery network (PDN) increasingly affects the power supply from the pads to the cells. Significant IR drops in standard cells can lead to timing violations, while suboptimal PDN topologies can lead to increased congestion. Together, these factors degrade overall chip performance and reliability. To accelerate design iteration, accurately and efficiently predicting unevenly distributed IR drop and congestion, especially in hotspot areas, has become a critical challenge. This article introduces an enhanced TransUNet-based framework for distribution-aware static IR drop and congestion prediction, treating both problems as separate but related image prediction tasks. Such an abstraction preserves the IR drop and congestion distribution patterns on the original real physical layout and retains local hot spots. Our proposed framework leverages image classification techniques to model IR drop prediction as a spatial pattern recognition task, effectively addressing the long-tail distribution in different regions. To enhance hotspot prediction, we incorporate wavelet transform and transformer-based analysis to enable multiscale feature fusion. In the open-source CircuitNet dataset, our method predicts static IR drop with a mean absolute error( MAE ) of 0.374 mV and a maximum error rate( Err m ) of 18.7%, reducing MAE and Err m by 77.4% and 79.2%, respectively, compared to the state-of-the-art method, all within 100 ms. The congestion prediction evaluations show 65.3% lower NRMSE scores and 18.4% higher SSIM scores relative to the existing SOTA approach. Our approach accurately and reliably predicts long-tail distributions and localized hotspots in both IR drop and congestion tasks.

As technology advances, the temperature gradient in the interconnects becomes more significant, which causes serious thermomigration. Simulating the coupling effects of thermomigration (TM) and electromigration (EM) on large-scale circuits is very time-consuming caused by a substantial increase in computational complexity. Recently, some researchers utilized graph learning-based methods to predict EM stress in medium-scale cases. Unfortunately, these works overlooked the effects of TM. To predict the EM - TM stress of large-scale interconnects accurately and efficiently, we propose a framework based on Graph Attention Networks (GATs) with a customized alternating aggregation method for collecting information in junctions and branches of interconnects jointly. The experimental results show that our work achieves an average relative error of less than 1 % compared to the commercial software COMSOL for inter-connects consisting of fewer than 200 segments. Furthermore, our method also achieves 9037 x speedup in predicting the OpenROAD test circuit with a maximum segment number reaching 10807.