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Demo Data from EDBT 2026 / reviewers in the wild / expert

Reshabh K. Sharma

dblp:369/3893 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2024
0009-0004-2678-9190ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
1 paper
Hardware security and side channels · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 100%
Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware security and side channels › microarchitectural side channel
microarchitectural timing channels		 0.812024
Avoiding Instruction-Centric Microarchitectural Timing Channels Via Binary-Code Transformations · ASPLOS (2) 2024
Processor architecture and microarchitecture
microarchitecture optimization		 0.812024
Avoiding Instruction-Centric Microarchitectural Timing Channels Via Binary-Code Transformations · ASPLOS (2) 2024

Methods — techniques the papers use, named apart from their topics

binary-code transformation · 2.3
YearPublicationVenuePosition
2024 Avoiding Instruction-Centric Microarchitectural Timing Channels Via Binary-Code Transformations
abstract
With the end of Moore's Law-based scaling, novel microarchitectural optimizations are being patented, researched, and implemented at an increasing rate. Previous research has examined recently published patents and papers and demonstrated ways these upcoming optimizations present new security risks via novel side channels. As these side channels are introduced by microarchitectural optimization, they are not generically solvable in source code.
Michael Flanders, Reshabh K. Sharma, Alexandra E. Michael, Dan Grossman, David Kohlbrenner
 ASPLOS (2)2