Synthesis tools can unlock the potential of analog architectures to achieve real-time computation, signal processing, inference and learning for low$S$WaP systems in commercial timescales. We present a methodology and results towards system analog and mixed-signal synthesis both for FPAAs and Custom Analog IC design. Building on previously efforts on large-scale Field Programmable Analog Arrays (FPAA) targeting tools enables tools capable of synthesizing new ICs. The IC synthesis is built upon our recent work on analog & mixed-signal programmable CMOS standard cell library that can be used across a range of CMOS process nodes (e.g. 180nm, 130nm, 65nm, 28nm, and 16nm CMOS). The entire tool-flow is being developed as an open-source tool that can be widely available. These approaches enable moving analog and mixed-signal design towards structured Design Space Exploration (DSE).

This effort describes a Python-based open-source tool to synthesize a mixed-signal reconfigurable IC fabric, known as large-scale Field Programmable Analog Array (FPAA) fabric. This tool starts from a high-level definition for an FPAA fabric to lower into gathered islands for each Computational Analog Blocks (CAB) and Computational Logic Blocks (CLB), and then extends the Ashes tool to first place and route each different island, and then place and route the full fabric. This tool integrates with the Ashes tool and expands both tools to enable synthesis of a configurable analog or mixed-signal reconfigurable fabric with other analog & mixed-signal standard cell components. The fabricated fabric could be targeted through the Ashes tool that integrates VPR into its place and route flow. The synthesis builds from recent innovations of programmable analog & mixed-signal standard cells that utilize Floating- Gate (FG) elements for their high-precision parameters. This effort demonstrates this synthesis entirely for 350nm standard cells with configurable chips that are synthesized to tapeout. These techniques generalize to other analog standard cell libraries (e.g. 130nm, 65nm, 16nm). A recent critical effort is the development of programmable analog & mixed-signal standard cells that utilize Floating-Gate (FG) elements for their high-precision parameters. These concepts, in-turn, enable the opportunity to both abstract higher levels of analog computation and enable large-scale analog synthesis.

This work presents an experimentally measured, implemented, openly-available programmable analog standard cell library in Skywater’s 130nm CMOS process. Programmability enables standard-cell components, eliminating the need for large number of device geometries required in classic analog design. This effort presents the methodology in developing these analog standard cell library and integrating synthesis with these cells.

Integrated circuit (IC) design for analog computing requires similar toolflows and synthesis as large-scale digital systems, in-turn necessitating a library of general-purpose analog cells. To this end, we present a programmable, floating-gate (FG)-based analog standard cell library in a commercially available 65 nm process that allows analog IC designers to use synthesis tools with an abstracted design mindset similar to large-scale digital design. We fabricate the test cells, which include filters with programmable corners, an analog classifier, and an arbitrary waveform generator (AWG); experimentally characterize FG programming; and experimentally demonstrate the performance of the standard cells. Overall, the standard cells achieve a similar or smaller footprint than previous approaches while leveraging the benefits of FG programming at smaller technology nodes.