State-of-the-art (SOTA) 3D physical design (PD) flows extend commercial 2D place-and-route (P&R) tools to enable signoff-quality 3D IC implementation through double metal stacking and inter-die metal layer sharing. While metal layer sharing introduces additional routing resources, the substantially higher manufacturing cost of face-to-face (F2F) inter-die vias compared to intra-die vias necessitates 3D-aware routing strategies to manage routability-cost trade-offs. To address this, we propose differentiable routing guidance for 3D ICs (DRG-3D), a GPUaccelerated differentiable optimization framework that provides routing guidance for 3D ICs. DRG-3D formulates a fully differentiable objective that simultaneously optimizes key 3D design metrics: routing congestion, wirelength, via cost, and F 2 F -via cost, which enables efficient and scalable gradient-based optimization over large-scale netlists. Experimental results show that DRG-3D outperforms the SOTA Pin-3D flow, achieving up to 8.37% reduction in routing overflow, 23.99% reduction in total negative slack (TNS), and 18.05% reduction in post-route timing violations.

IR drop analysis in the power delivery network (PDN) is crucial for the signoff of integrated circuit (IC) design. Static IR drop significantly affects the IC reliability. Machine learning (ML) has recently been applied to static IR drop prediction for its high accuracy and efficiency. However, most previous works cannot predict with unseen designs, and none can handle different technologies. These problems lead to long training times and data-gathering difficulties, making ML-based methods impractical in the industry. Therefore, a more applicable methodology for static IR drop predictions is needed. This paper proposes a fast, robust, highly technology-transferable image-to-image ML-based methodology for static IR-drop prediction. To enhance transferability and accuracy, we introduce a new input feature, layerwise maps, which encapsulates the PDN network topology well. We further derive a novel generic ML model for various designs and technologies with different numbers of PDN layers. Experimental results demonstrate our methodology's high accuracy, robustness, and technology transferability. We used only ten circuits to tune our pre-trained model on a new technology and achieved an average error rate of 10.4% IR drop value on unseen circuits. Additionally, we tuned our pre-trained model for the 2023 ICCAD CAD Contest. Compared to the contest winner, our method gets a comparable average error rate of 0.000152mV with a run time of less than 1.5 seconds and improves the MAE of the worst case by 29.7%.

State-of-the-art 3D IC flows fail to consider 3D congestion during earlier stages, leading to excessive use of end-of-flow ECO resources for routability correction that severely degrades full-chip Power, Performance, and Area metrics. We present DCO-3D, a Machine Learning-based routability-aware 3D PD flow that performs early post-route congestion prediction using Siamese Networks and resolves the predicted hotspots using a fully differentiable 3D cell spreading with Graph Neural Network. On 6 industrial designs in a commercial 3nm node, DCO-3D improves Pin-3D, the known best Pin-3D flow, by up to 47.2% in overflow, 86.2% in TNS and 5.1% in power at signoff.

Probabilistic error cancellation (PEC) is a promising error mitigation technique that reduces the error rate without auxiliary quantum bits. However, PEC has two problems that need to be resolved: 1) there is no good PEC technique for parameterized gates and 2) sampling overhead (SO) grows exponentially with the number of PEC mitigated gates. We first propose a parameterized gate PEC (PGPEC) that mitigates the error without fully characterizing the gates, as the original PEC requires. The result shows that the number of gates requiring characterization for a thousand random circuits can be reduced by 97% or more. We next propose two novel approaches to solving the second problem. We propose a macro gate PEC (MGPEC) technique that aggregates multiple gates as a single macro gate to reduce the exponent of the SO. MGPEC reduces the SO by 49% on the QFT7 under the IBMQ noise model, which simulates real operation conditions of quantum circuits. We propose a design diversity PEC (DDPEC) technique to reduce the exponential basis of the SO. The results show that our DDPEC with design diversity check reduces overall SO by 13% on the QFT7 circuit under the IBM Q noise model. Combining the DDPEC with the MGPEC, we can reduce overall SO by 73%.