This paper presents a novel method named the Unified Mitchell-based Approximation (UMA) to obtain an optimized Mitchell-based logarithmic conversion circuit for any desired conversion accuracy up to 14 bits. UMA is the first method that is able to obtain a conversion circuit when a specific accuracy is required. In this work, we studied and analyzed five design parameters and their impact on accuracy and hardware merits. We formulate the hardware model of the error correction circuit in the conversion circuit for performance evaluation. Given an accuracy requirement, the proposed method explores the design space of the five design parameters. As the design space is theoretically huge, we propose constraints for the range of the parameter values and develop a systematical search algorithm for exploring the design space. UMA is able to obtain an area-delay product optimized circuit for each of the conversion accuracies achieved by the existing Mitchell-based designs. Synthesis results in 90 nm CMOS technology show that the circuits obtained are comparable or better than the existing Mitchell-based designs with the same accuracy objective. Nine of the fifteen circuits obtained achieve better area-delay product by more than 50 percent. In addition, UMA is able to obtain circuits for any accuracy from 4 to 14 bits, while the best accuracy achieved by the existing Mitchell-based methods is less than 12 bits.

A novel non-iterative circuit for computing division based on logarithm is proposed in the paper. Mitchell-based methods are used for the logarithmic and antilogarithmic conversions. Merging the conversion stages in the implementation is not possible if the existing antilogarithmic conversion algorithms are used. Thus, the critical path has at least two carry propagate adders (CPAs). This work introduces a new antilogarithmic algorithm to merge the two conversion stages into a single one to remove one of the two CPAs. Compared to the best existing Mitchell-based logarithmic division computation method used in a 3-D graphic system, the proposed design achieves improvements by 45.4% and 34.8%, respectively, in computation speed and area-delay product with an area overhead of 19.5%.

The tables-and-additions methods for accurate computation of elementary functions are fast in computation speed but require large memory. A memory-efficient method named as the integrated Add-Table Lookup-Add (iATA) is proposed in this paper. In iATA, the mathematical formulation for computing the elementary functions is derived without using the central difference formulation to save memory. Three additional techniques, specifically the carry select technique, symmetry property exploitation and unequal partitioning of input with the aid of error analysis, are integrated in iATA to further reduce the memory size. The experimental results show that the proposed method is able to achieve higher memory efficiency than the best existing tables-and-additions methods. For the reciprocal and the natural logarithm function, iATA saves 23.63 and 61.39 percent of memory when compared to the best existing results obtained, respectively, by the unified Multipartite Table Method [39] and the Symmetric Table Addition Method [37].

A novel non-iterative circuit for computing integer square root based on logarithm is proposed in the paper. Mitchell's methods are used for the logarithmic and antilogarithmic conversions. The proposed method merges two conversion stages into a single one to achieve better accuracy with a compact architecture. Hence, the circuit size and latency are reduced. Compared to an existing design based on the modified Dijkstra algorithm used in a coherent receiver, the proposed design is either 8 times smaller or 9 times faster for 16-bit integer input.