In low power designs, timing-speculative techniques are proposed to boost the SRAM frequency and throughput. This paper proposes TYMER, a unified yield-based performance model for timing-speculative SRAM. In TYMER, the first sub-model evaluates access-time yield at different worldline enable time for a general 6T SRAM under low supply voltages, while the second one uses the yield results to estimate optimal sensing time and the overall read latency for speculative SRAM. TYMER is not only compared with simulation results but also the measurements from 28nm fabricated speculative SRAM chips. Both cases show precise evaluation results under different operating conditions.

Statistical SRAM yield analysis has become a growing concern for the requirement of high integration density and reliability of SRAM under process variations. It is a challenge to estimate the SRAM failure probability efficiently and accurately because the circuit failure is a "rare-event". Existing methods are still not efficient enough to solve the problem, especially in high dimensions. In this paper, we develop a scaled-sigma adaptive importance sampling (SSAIS) which is an extension of the adaptive importance sampling. This method changes not only the location parameters but the shape parameters by searching the failure region iteratively. The 40nm SRAM cell experiment validated that our method outperforms Monte Carlo method by 1500x and is 2.3x~5.2x faster than the state-of-art methods with reasonable accuracy. Another experiment on sense amplifier shows our method achieves 1811x speedup over the Monte Carlo method and 2x~11x speedup over the other methods.