Demo Data from EDBT 2026 / reviewers in the wild / expert
Aditya Rajeev Kulkarni
dblp:37/1856
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2004
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
1 paper |
Program analysis · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 77% Embedded and real-time systems · 23% |
Topics — the 3 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Program analysis › static analysis
program slicing |
0.0 | 1 | 2004 | Slicing tools for synchronous reactive programs · ISSTA 2004 |
Program analysis
static analysis |
0.0 | 1 | 2004 | Slicing tools for synchronous reactive programs · ISSTA 2004 |
Electronic design automation › hardware verification and test
hardware verification |
0.0 | 1 | 2004 | Slicing tools for synchronous reactive programs · ISSTA 2004 |
Methods — techniques the papers use, named apart from their topics
static slicing · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2004 | Slicing tools for synchronous reactive programsabstractIn this paper, we present two slicing tools: VHDL_Slice and Est_slice that compute static executable slices of VHDL and Esterel programs respectively. The slicers have been tested on a number of small and medium sized examples. S. Ramesh 0001, Aditya Rajeev Kulkarni, Viraj Kamat |
ISSTA | 2 |