Demo Data from EDBT 2026 / reviewers in the wild / expert
Chang-Ching Wu
dblp:37/1937
· DBLP profile ↗
3ranked-venue papers
2as first author
0since 2021 · last 2010
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 50% Embedded and real-time systems · 50% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design › analog and mixed-signal circuits
analog circuit design |
0.1 | 1 | 2009 | Contract-based system-level composition of analog circuits · DAC 2009 |
Embedded and real-time systems › embedded system design
platform-based design |
0.1 | 1 | 2009 | Contract-based system-level composition of analog circuits · DAC 2009 |
Methods — techniques the papers use, named apart from their topics
contract-based design · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2010 | A 2.2mW CMOS LNA for 6-8.5GHz UWB receiversabstractThis paper presents an ultra-wideband (UWB) low noise amplifier (LNA) consuming 2.2-mW core dc power for 6-8.5GHz wireless applications. A common-gate input stage is cascaded with a common-source second stage to perform input impedance matching and wideband stagger-tuning amplification, while the current-reuse topology minimizes the dc power dissipation. The design method used to achieve flat-gain response is presented. A detailed analysis gives insight into the issue on the input impedance and suggests a solution. Implemented in a 90-nm CMOS process, the measurement results show power gain of 13.35+/-0.55 dB, input third intercept point (IIP3) of-6.2 dBm, and noise figure of 5-6.5 dB. The silicon die with 0.22-mm2active area allows the design to be adopted for highly integrated low-cost CMOS applications. Chang-Ching Wu, Xuening Sun, Alberto L. Sangiovanni-Vincentelli, Jan M. Rabaey |
ISCAS | 1 |
| 2009 | Contract-based system-level composition of analog circuitsabstractEfficient system-level design is increasingly relying on hierarchical design-space exploration, as well as compositional methods, to shorten time-to-market, leverage design re-use, and achieve optimal performances. However, in analog electronic systems, circuit behaviors are so tightly dependent on their interface conditions that accurate system performance estimations based on characterizations of individual stand-alone circuits is a hard task. Since there is no general solution to this problem, analog system integration has traditionally used ad-hoc solutions heavily dependent on designers' experience. In this paper, we build upon the analog platform-based design methodology by exploiting contracts to enforce correct-by-construction system-level composition. Contracts intuitively capture the thought process of a designer, who aims at guaranteeing circuit performance only under specific assumptions (e.g. loading and dynamic range) on the interface properties. Our approach allows automatic detection and composition of compatible components in a given library. We apply our methodology to an ultra-wide band receiver front-end to show that contracts allow pre-designed IP components to be smoothly integrated and design decisions to be reliably made at a higher abstraction level, both key factors to improve designer productivity. Xuening Sun, Pierluigi Nuzzo 0002, Chang-Ching Wu, Alberto L. Sangiovanni-Vincentelli |
DAC | 3 |
| 2006 | A 0.13µm CMOS T/R switch design for ultrawideband wireless applicationsabstractA CMOS transmit-receive (T/R) switch design for ultrawideband (UWB) wireless applications is presented. A shunt inductor is adopted in the T/R switch signal path to improve the insertion loss (IL) and work as electrostatic discharge (ESD) protection device. Two bypassing switches at the gate of the main switching transistors provide additional isolation. Control voltage as low as 1.2V is applied to handle the T/R switch operation. Implemented in UMC 0.13/spl mu/m MMRF CMOS technology, the measured results show an IL of 0.78-0.99dB in the receive (RX) mode and an isolation from TX port to RX port higher than 30.8dB in the transmit (TX) mode in the 3.1-4.8GHz frequency range. The measured ESD rating is 3kV HBM. The T/R switch is designed for monolithic integration with UWB RF front-end building blocks. The on-chip inductor eliminates the need of an off-chip one for the wideband matching network. Chang-Ching Wu, A. Yen, Jen-Chung Chang |
ISCAS | 1 |