In recent years, camera identification methods have attracted attention in the field of digital forensics. The existing camera identification methods use features, such as the Exif header data and image noise, that indicate the characteristics of the camera. Of them, photo-response non-uniformity (PRNU) noise contains the unique features of an image sensor and is different for each individual camera. A camera identification method using the PRNU noise should have high identification ability, and a camera identification method using the pairwise magnitude relations of the clustered PRNU noise was previously proposed. In general, identification accuracy is estimated from test data sets, such as the Dresden image database. However, identification accuracy can be evaluated only with respect to the range of images within a database in the conventional evaluation method. A more detailed accuracy evaluation method is required for practical use. Furthermore, studies have not yet reported a false acceptance rate (FAR) evaluation method for the clustered PRNU pair-based camera identification capable of guaranteeing a low FAR (e.g., FAR = 10-9). In this paper, we proposed a new pixel clustering method that guarantees An FAR for camera identification using pairs of clustered PRNU noise, and evaluate its FAR based on a probability calculation of a mathematical model. In addition, we investigate the appropriate cluster size by using the Shapiro-Wilk test for an FAR evaluation. We show that it is possible to reliably calculate the FAR of a clustered PRNU noise pair-based camera identification method by using the proposed evaluation method. To demonstrate the validity of our calculations, we compare the actual identification result with the result of the proposed calculation. In this case, we used 16958 query images from the Dresden image database, which is a benchmark data set. The results of our evaluation indicate that this identification method maintains a false rejection rate of less than 5% (10%) for 5 (8) of the 10 tested cameras even for FAR = 10-9.

Field-programmable gate arrays (FPGAs) are extremely advanced with regard to high performance; they are becoming one of the primary device choices to realize high-performance computing (HPC). In this work, we propose an FPGA-based accelerator for the two-dimensional (2D) finite difference method (FDM) with the implicit scheme and implement a 2D unsteady-state heat conduction simulation using red/black successive over-relaxation (SOR). The accelerator consists of a 2D single-instruction multiple-data (SIMD) array processor, which has pipelined processing elements (PEs) including 32-bit floating point calculation units. This processor can avoid the memory-access bottleneck and perform with high operating efficiency and low waiting time for data transfer by applying the proposed control method with synchronous shift data transfer. We demonstrate that the experimental hardware implemented on an Altera Stratix V FPGA (5SGSMD5K2F40C2N) reaches a 99.83% operating rate of the calculation units for the computation of red/black SOR. In addition, it is approximately six times faster than GPU computing on an NVIDIA GeForce GTX 770 for a 32-bit floating-point calculation of a printed circuit board (PCB) heat conduction simulation, and it is about eight times faster than an NVIDIA Tesla C2075 for the same calculation.

Worldwide, many surveillance systems are in operation for crime deterrence purposes. An effective system should be characterized by requiring low-power consumption, a small storage capacity, and little human effort. Multi-stream tracking on field programmable gate array (FPGA) is important for such surveillance systems. In this paper, we propose multi-stream tracking hardware that can extract moving objects and their motion vectors from a multi-stream received from 64 cameras in real time. The key technology for multi-stream processing is as follows. (1) In order to avoid maintaining the background, we apply a frame difference method. Moreover, the flows of object are calculated by block matching. The flows are effective for analyzing human motion. (2) In order to avoid a bus bottleneck and memory contention in the communication between processing elements (PEs), synchronous shift data transfer (SSDT), which transfers data in the same direction for all PEs, is applied. In this paper, an extended SSDT is proposed for communication between PEs when multi-blocks are processed in one PE. (3) C++ based integrated control code development tool is shown. Control code written in C++ language can easily be assembled and verified by the tool. We implemented the proposed hardware on a Stratix V 5SGXEA7K2F40C2N device. The operating frequency is 50 MHz and the average number of clocks for processing a set of four frames of QVGA images is 394k clocks. The proposed hardware achieved 520 fps, and can process multi-stream video from 64 cameras. The execution time on 3.4 GHz Core i7-3770 CPU was 8.4 fps. Therefore, the proposed hardware was about 62 times faster than that CPU.

Three-dimensional (3D) numerical simulation is an indispensable technique for various analyses of physical phenomena, but it generally requires numerous computation. In this paper, we propose an FPGA-based accelerator for 3D numerical simulations and focus on acceleration of the 3D finite-difference time-domain (FDTD) method. This accelerator consists of a 2D single instruction multiple data (SIMD) array processor, and it can execute 3D parallel computing with little data transfer overhead by applying virtual processing-elements cuboid (VPEC) with synchronous shift data transfer. We demonstrate that the experimental hardware implemented on an Altera Stratix V FPGA (5SGSMD5K2F40C2N) is 3.1 times faster than parallel computing on the NVIDIA Tesla C2075, and it reaches a 94.57% operating rate of the calculation units for the computation of the 3D FDTD method. The proposed accelerator is suitable for multi-chip composition.

Mobile surveillance robots are being used for practical applications, and such mobile robots have gathered attention as an attractive option for video surveillance systems. Several methods for patrol course planning have been proposed, and these methods can generate optimum/approximate patrol courses with certain objectives and conditions such as minimization of observation intervals and the number of cameras. However, these patrol plans do not consider energy consumption. In actual operation, we must consider the power consumption and battery station placement. It is possible to reduce the costs of surveillance systems by reducing the number of battery stations. In this paper, we propose a method for obtaining a patrol course that satisfies the observation constraint, and an optimum location of battery stations, simultaneously. The effectiveness of the proposed method is demonstrated by applying it to some practical examples of airports and towns.

Patrolling by mobile robots is an attractive option for enhancing the reliability of video surveillance systems; mobile robots can observe a wide area effectively during particular intervals, which helps in the early detection of fires and other unusual situations. Moreover, if mobile robots patrol so that anymoving objects cannot exist without being observed, such patrol can be helpful in detecting suspicious individuals. In this paper, we propose a method for determining the minimum number of mobile surveillance cameras and their patrol plans that can realize periodic observation of all regions and moving objects. We demonstrate that we can obtain short patrol courses to achieve reliablemonitoring in our experiments.

Owing to the rapid progress in digital camera technologies, a large amount of image content is distributed on the World Wide Web. Digital camera identification, which is the identification of the source camera of an input image, is becoming increasingly important for presenting evidence in a court and helping police investigations. In recent years, a digital camera identification method using the image sensor's pattern noise has received considerable attention. Photo-response non-uniformity (PRNU) noise is mainly generated by the existence of differences between the sensitivities of pixels, and it is useful as a fingerprint of a camera. However, the PRNU noise of an image is usually contaminated by random noise and scene content and affected by the image processing engine, which inhibits stable identification. In this paper, we propose a novel digital camera identification method using the pairwise magnitude relations of image sensor noise, which are robust to noise contamination. By performing experiments, we demonstrate that the proposed method can identify the source cameras of query images with high accuracy.

Video surveillance systems are becoming increasingly important for crime investigation and deterrence, and the number of cameras installed in public space is increasing. However, many cameras installed at fixed positions are required to observe a wide and complex area. In order to efficiently observe such a wide area at lower cost, mobile robots are an attractive option. In this paper, we propose a method for determining the traveling route of a mobile surveillance camera. Our method is based on mixed integer linear programming and obtains an optimum traveling route such that a camera with a certain visual angle and visual distance can observe the entire region at the shortest intervals. Through our experiments, we apply this method to several artificially generated data and data for a real university campus and demonstrate that effective patrol courses for specified mobile surveillance cameras can be generated.

Along with the popularization of digital cameras, the reliable identification of digital image source is becoming increasingly important as an evidence in a court and some help of investigations. In this paper, we propose an enhanced digital camera identification method using the pixel non-uniformity (PNU) noise of image sensors. By clustering the PNU noises, the proposed method extracts the robust features of image sensors to the random noise, scene content, and image processing engine such as the noise reduction. In the experiments, the proposed method shows the high identification accuracy even for latest digital cameras.

We present an optimum camera placement algorithm. We are motivated by the fact that the installation of security cameras is increasing rapidly. From the system cost point of view, it is desirable to observe all the area of interest by the smallest number of cameras. We propose a method for deciding optimum camera placement automatically considering camera specification such as visual distance, visual angle, and resolution. Moreover, to reduce the number of cameras, we divide the scene into regions and weight them according to their importance of observation. Then, we calculate camera locations which cover all the important regions and as many other regions as possible by considering the trade off between a number of observed regions and the number of cameras required. We formulate this problem as a set covering problem.

We have succeeded in developing a quick and fully automated system that can generate photo-realistic 3D CG data based on a real object. A major factor in this success comes from our findings through psychophysical experiments that human observers do not have an accurate idea of what should be actually reflected as inter-reflections on the surface of an object. Taking advantage of this characteristic of human vision, we propose a new inter-reflection representation technique in which inter-reflections are simulated by allowing the same quantity of reflection components as there are in the background to pass through the object. Since inter-reflection and transparency are calculated by the same algorithm, our system can capture 3D CG data from various real objects having a strong inter-reflection, such as plastic and porcelain items or translucent glass and acrylic resin objects. The synthetic images from the 3D CG data generated with this pseudo inter-reflection and transparency look very natural. In addition, the 3D CG data and synthetic images are produced quickly at a lower cost.

3D object data transfer was optimized to accelerate interactive 3D scene design and virtual-space layout applications. In these applications, downloading many 3D objects reduces the interactivity of the clients. We used level-of-detail based loading sequences and timing control methods to interleave data downloading and interactions. Experiments showed that the maximum interval between interactions was up to 6.42 times shorter.

This paper proposes an efficient paired-net routing algorithm. A paired net consists of two nets assigned to adjacent tracks and columns. The paired-net routing approach is applied for differential drive nets in a bipolar ECL LSI to decrease signal skew and enhance signal integrity. Paired nets can cause a new type of cyclic constraint, which does not appear in the conventional vertical constraint graph. To wire these paired nets, the new type of cyclic constraint must be detected and resolved. We applied our approach to two actual bipolar ECL circuits: a 4.0-k-gate circuit, which operated at 3 Gbit/s, and a 5.6-k-gate circuit, which operated at 2.5 Gbit/s. The experimental results verify the effectiveness of our paired-net routing approach.

A timing-driven global routing algorithm applicable to high-speed bipolar LSI's is proposed. Path-based timing constraints are directly modeled and routing paths are selected using novel heuristic criteria to minimize area as well as to satisfy the timing constraints by keeping track of the critical path delay and channel densities. Using bipolarspecific features, this router can be applied to Gbit/s LSI's. Experimental results shows that the average delay improvement was 17.6% and the algorithm is quite promising.

Global and detailed routing algorithms that minimize crosstalk noise between signal lines are described. In mixed analog/digital circuits, crosstalk noise causes chip performance degradation. Thus, the proposed global routing algorithm routes analog nets in the independent area of the digital nets as much as possible. Both the global and detailed routers minimize the number of signal-line crossovers, especially for analog nets, as these crossovers are dominant in crosstalk noise. Double width lines can be used to avoid unexpected voltage drops caused by parasitic resistances. A postprocess automatically puts up shield lines for very noise sensitive wirings to improve the S/N ratio. The experimental results show that the proposed algorithms are effective in reducing the number of crossovers and redundant vias.>

A new parallel-processing wire-routing algorithm is presented and implemented on a parallel processor. The two main features of the parallel algorithm are the control of the path quality and the finding of a quasi-minimum Steiner tree. Both Lee's maze algorithm and the proposed algorithm are implemented on an AAP-1 two-dimensional array processor, and the performance is compared to that of software programming on a general-purpose computer. It is shown experimentally that routing by the proposed algorithm implemented on the AAP-1 is 230 times faster than a software maze router run on a 1-MIPS computer for a three-pin/net circuit on a 256 X 256 grid.

In a hierarchical VLSI layout design, the block-level layout design is called a "chip floor plan." In this paper, a semi-automatic VLSI chip floor plan algorithm and its implementation are presented. The initial block placement is obtained by an attractive and repulsive force method (AR method), and the subsequent block packing process is performed by gradually moving and reshaping blocks with chip boundary shrinking. The chip area estimation is performed by using individual block area calculations from empirically obtained equations. A set of interactive commands is also provided to facilitate the manual optimization processes using a color graphic terminal. By processing several practical VLSI circuits, it is shown that the method is very effective for handling various kinds of blocks and is able to reduce the design effort required to achieve the chip floor plan.

A new hierarchical top-down layout design system for custom VLSIs has been developed. A top-down global route assignment process reduces the redundant wiring area. Routing in a single path over the whole chip enables efficient chip area use.