In the task of multi-label aerial image classification, various objects and land cover in an image are usually represented by multiple labels which are treated equally. However, from a semantic point of view, the importance of multiple labels are different in a specific scene. There is often a prime label in the image that plays a "leading" role. Obtaining the most important label from candidate multiple labels is crucial, because it best represents the semantics of the entire image. In this letter, we attempt to automatically obtain the prime label of each image from several existing multi-label aerial image datasets without additional supervision cost. In other words, the prime labels are only used to evaluate the performance of models during testing and do not participate in the training process. Therefore, it is essentially a weakly supervised learning task. For this novel aerial image classification task, corresponding datasets are provided in this letter firstly, including over head images with multi-labels for training and prime labels for testing. Then the baselines on the above datasets are provided. Finally, a new prime label learning method is proposed, which improves the baseline accuracy by about 14% and reaches the state-of-the-art on current datasets.

Recently, the research of performance prediction with prior knowledge obtained by machine learning (ML) techniques has been widely studied. In this paper, we present the first work of machine learning framework using complex network features to predict wire-length in physical design. The experimental result on TAU 2017 Benchmark shows the effectiveness and efficiency of our method. The predictors based on four machine learning models provide a high accuracy and reasonable speed compared with normal EDA (Electronic Design Automation) tool.

Most traditional approaches classify hyperspectral image (HSI) pixels relying only on the spectral values of the input channels. However, the spatial context around a pixel is also very important and can enhance the classification performance. In order to effectively exploit and fuse both the spatial context and spectral structure, we propose a novel two-stream deep architecture for HSI classification. The proposed method consists of a two-stream architecture and a novel fusion scheme. In the two-stream architecture, one stream employs the stacked denoising autoencoder to encode the spectral values of each input pixel, and the other stream takes as input the corresponding image patch and deep convolutional neural networks are employed to process the image patch. In the fusion scheme, the prediction probabilities from two streams are fused by adaptive class-specific weights, which can be obtained by a fully connected layer. Finally, a weight regularizer is added to the loss function to alleviate the overfitting of the class-specific fusion weights. Experimental results on real HSIs demonstrate that the proposed two-stream deep architecture can achieve competitive performance compared with the state-of-the-art methods.

With the increasing risk of IP reuse in System on Chip (SoC) design, intellectual property (IP) techniques becomes one of the most important issues. Compare with watermarking, fingerprinting is a more effective method because is not only protects the IP owner's benefits but also user's rights. In this paper, we firstly propose a multilevel fingerprinting method for IP protection. In the typical field programmable gate array (FPGA) design flow, we first embed the watermarks into a FPGA design at netlist level by manipulating LUTs. When the IP core is compiled into a bitstream file, an individual fingerprint from IP user is then embedded into margin of FPGA. The experimental results show that the method has low resource and timing overhead, while proves a strong certificate both of IP owner and users.

In this paper, we introduce a new watermarking system for IP protection on post-layout design phase. Firstly the copyright is encrypted by DES (Data Encryption Standard) and then embedded by using an incremental router into the layout design. This watermarking technique uniquely identifies the circuit origin, yet is difficult to be detected or fabricated. The incremental router consists of a rip-up and a special re-router that inserts redundant bends into wires probabilistic. We evaluated the technique on various generated benchmark circuits to validate the completeness of the procedure. The results show it achieves almost 100% success for embedding with no extra area cost on design performances.