Abstract Fin Field-Effect Transistor (FinFET) technology enables the continuous downscaling of Integrated Circuits (ICs), using the Complementary Metal-Oxide Semiconductor (CMOS) technology in accordance with the More Moore domain. Despite demonstrating improvements on short channel effect and overcoming the growing leakage problem of planar CMOS technology, the continuity of feature size miniaturization tends to increase sensitivity to Single Event Upsets (SEUs) caused by ionizing particles, especially in blocks with higher transistor densities such as Static Random-Access Memories (SRAMs). Variation during the manufacturing process has introduced different types of defects that directly affect the SRAM's reliability, such as weak resistive defects. As some of these defects may cause dynamic faults, which require more than one consecutive operation to sensitize the fault at the logic level, traditional test approaches may fail to detect them, and test escapes may occur. These undetected faults, associated with weak resistive defects, may affect the FinFET-based SRAM reliability during its lifetime. In this context, this paper proposes to investigate the impact of ionizing particles on the reliability of FinFET-based SRAMs in the presence of weak resistive defects. Firstly, a TCAD model of a FinFET-based SRAM cell is proposed allowing the evaluation of the ionizing particle’s impact. Then, SPICE simulations are performed considering the current pulse parameters obtained with TCAD. In this step, weak resistive defects are injected into the FinFET-based SRAM cell. Results show that weak defects can positively or negatively influence the cell reliability against SEUs caused by ionizing particles.

The miniaturization of CMOS technology is likely to reach its limit due to short-channel effects. New transistor technologies, including FinFET technology, were developed to deal with this effect and enable the continuous scaling-down of technological nodes. Alongside the constant scale-down of integrated circuits technology, the increasing need to store more and more information has resulted in the fact that Static Random Access Memories (SRAMs) occupy great part of Systems-on-Chip (SoCs). The manufacturing process variation has introduced different types of defects that directly affect the SRAM's reliability. Thus, it remains unknown if fault models used to characterize faults in CMOS memory circuits are sufficiently accurate to represent the behavior of FinFET-based memories. In this context, a study of functional implications of manufacturing resistive defects in FinFET-based SRAMs is presented. In more detail, a fault model for FinFET-based SRAMs as well as a complete analysis of the static and dynamic fault behavior are presented. The proposed analysis has been performed by means of SPICE simulations, adopting a 20nm technology library. The faults were categorized in single and coupling, static and dynamic faults.

This work explores the concept of design diversity redundancy applied to mixed-signal (MS) circuits. Results from fault injection experiments show a very good ability of the system to tolerate double faults.

Programmable analog devices are susceptible to radiation effects. TID effects are a matter of concern due to the thickness of oxides in common analog technologies and can be mitigated by HBD techniques and shielding. SEEs may also disturb programmable analog devices, and system level techniques based on on-line error detection and self-correction may be applied by using the available programmable resources of the device.

In this work a strategy for testing analog networks, known as transient response analysis method, is applied to test the configurable analog blocks (CABs) of field programmable analog arrays (FPAAs). In this method the circuit under test (CUT) is programmed to implement first and second order blocks and the transient response of these blocks to known input stimuli is analyzed. Taking advantage of the inherent programmability of the FPAAs, a BIST-based scheme is used in order to obtain an error signal representing the difference between fault-free and faulty CABs. Different functions available in the component programming library are studied and a choice is made in order to obtain the best results in terms of sensitivity and test coverage. A functional fault model based on high-level parameters of the transfer function of the programmed blocks is adopted and the relationship between these parameters and CAB component deviations is investigated, therefore allowing to estimate the fault coverage and test application time of the proposed functional test method

The test of field programmable analog arrays (FPAA) may be performed based on partitioning these devices in three main parts: I/O cells, interconnection networks and configurable analog blocks. In this work, a scheme for testing the I/O cells and the local and global interconnection networks of FPAAs is proposed, using an adjacency graph model to represent the programmable interconnection and I/O resources, and then devising a set of test configurations (TC) by solving graph coloring problems. The goal is to achieve a near minimum number of TCs ensuring all stuck-open and stuck-on faults in switches, as well as opens and shorts in wires, are covered. Large parametric faults in interconnects are implicitly covered in these TCs by judiciously choosing test stimuli and, in I/O buffers, by means of an oscillation-based test strategy.

The problem of testing the configurable analog blocks (CABs) of field programmable analog arrays (FPAAs) is addressed in This work. The considered fault model comprises deviations in the nominal values of CAB programmable capacitors, deviations in the programmable gains of CAB input amplifiers and stuck-on/stuck-open faults in CAB switches. The problem of test stimuli generation is solved, in a first approach, by using the oscillation test strategy (OTS), which is associated to a test response analysis external to the device under test. In a second approach, a built-in self-test (BIST) scheme is proposed by associating to the OTS an output response analyzer (ORA) built using the internal FPAA resources. Both approaches are validated using the ispPAC10 FPAA from the Lattice Semiconductor Corporation. In the paper, the approaches are compared in terms of fault coverage, test application time and required external hardware resources for testing. Experimental results show that a good compromise of these aspects can be found by taking the best of each approach.

The use of the oscillation test strategy to test configurable analog blocks of field programmable analog arrays (FPAAs) has been proposed previously, solving the complex problem of test stimuli generation. An improvement to that technique is presented in this paper, using the resources of the FPAA to build an output response analyzer. This new approach offers a full built-in self-test scheme with no area overhead and requiring a low cost automatic test equipment. Experiments show the efficiency of the approach in detecting parametric faults of the tested components.