Successful reverse engineering (RE) of digital signal processing (DSP) integrated circuits (ICs) by an attacker provides him/her a chance to pirate the DSP-based intellectual property (IP) and insert malicious logic. It is thus central to devise low-cost sturdy functional obfuscation techniques for DSP cores that hinders RE attempt (or increases attackers effort manifold). There has been meager effort on devising robust high-level synthesis (HLS) based functional obfuscation methodology that is low-cost/power. This paper presents a novel S ecure Hi gh- L evel synthesis based functional obfuscation methodology for E nhanced security of D SP cores called “ SHiELD ” that is driven through HLS based one-way random (OWR) function and reconfigurable composite switching obfuscation (CSO) cells, integrated with design space exploration process. The proposed approach offers security against different relevant attacks and in overall effectively thwarts RE attempt with the aid of proposed multi-key bit CSO cells, and custom OWR function. The results of the proposed approach in comparison with prior approaches yielded several magnitudes of higher security (robust obfuscation strength and lower probability of key retrieval) upto ∼10 154 (for FIR-2 benchmark calculated using Equation ( 1 )), lower power (of ∼10.6%) and reduction in design cost (of 0.91%).

Reusable third-party intellectual property (3PIP) cores within the supply chain are vulnerable to hardware threats such as IP piracy and false claim of ownership. Securing the reusable IP cores is vital to protect the original vendor from a substantial revenue loss and his/her brand value. This paper presents a novel hardware IP core watermarking methodology based on voice biometric signature to enable detective control against IP piracy and resolve IP ownership claim. To the best of our knowledge, this is the first voice biometric-based hardware IP protection technique. This paper proposes a novel methodology for generating a unique voice signature template using distinct voice features, viz. jitter and shimmer, along with pitch and intensity values at different timestamps. We present a high-level synthesis (HLS) design methodology of embedding a voice signature digital template during the register allocation phase to generate secured IP cores. Results and analysis imply that the proposed approach can significantly improve security in terms of stronger authorship proof and higher tamper tolerance compared to the existing IP watermarking approaches. Additionally, we also analyze the uniqueness of a voice signature and its security against forgery attack. We achieve higher security at negligible design cost overhead.

This paper presents a novel hardware security technique that leverages handwritten signature image features for securing intellectual property (IP) cores, such as digital signal processing (DSP) cores, against IP piracy and false claim of IP ownership threats. In our approach, an IP vendor's handwritten signature image features are first converted into a corresponding digital template, followed by mapping into hardware security constraints and implanting them into the design during high level synthesis (HLS) process. This paper presents methodologies of extracting feature set of a handwritten signature through sampling and of encoding of the samples into binary values using a tree based encoding, for generating the digital template. The results of the proposed approach are assessed in terms of strength of IP ownership proof, security against a forged signature and impact of embedding signature constraints on design cost. The results revealed that the proposed approach provides robust security at negligible design cost overhead and also outperforms state of the art hardware security approaches for DSP cores.

This article proposes a robust encrypted protein molecular biometric signature-based hardware security approach to secure hardware accelerators (like digital signal processing (DSP) and multimedia intellectual property (IP) cores) against threats of piracy/IP counterfeiting and ownership abuse. In the proposed approach, protein molecular biometric signature is formulated by taking the protein sequence of 20 different unique amino acid combinations from human body protein sample, followed by robust encryption using facial biometric key and encodings. This IP vendor’s encrypted protein molecular biometric signature is then subsequently converted into its corresponding digital proof, followed by embedding into the design as a covert protein molecular signature security constraint, thus producing a secured hardware accelerator design. The proposed approach is more robust than recent hardware security approaches proposed in the literature in terms of stronger proof of ownership (authorship) as well as tamper tolerance (TT) ability. The results present the following analysis of the proposed protein molecular biometric signature approach: 1) very low probability of coincidence (Pc) metric (signifying strength of digital proof) for different DSP hardware accelerators in the range of 3.40E-13–6.33E-2 and 2) stronger TT ability in the range of 5.39E + 67–1.0E + 421 for different DSP hardware accelerators.

Hardware security and trust have become a pressing issue during the last two decades due to the globalization of the semiconductor supply chain and ubiquitous network connection of computing devices. Computing hardware is now an attractive attack surface for launching powerful cross-layer security attacks, allowing attackers to infer secret information, hijack control flow, compromise system root-of-trust, steal intellectual property (IP), and fool machine learners. On the other hand, security practitioners have been making tremendous efforts in developing protection techniques and design tools to detect hardware vulnerabilities and fortify hardware design against various known hardware attacks. This article presents an overview of hardware security and trust from the perspectives of threats, countermeasures, and design tools. By introducing the most recent advances in hardware security research and developments, we aim to motivate hardware designers and electronic design automation tool developers to consider the new challenges and opportunities of incorporating an additional dimension of security into robust hardware design, testing, and verification.

This article presents a novel facial biometrics-based hardware security methodology to secure hardware accelerators [such as digital signal processing (DSP) and multimedia intellectual property (IP) cores] against ownership threats/IP piracy. In this approach, an IP vendor's facial biometrics is first converted into a corresponding facial signature representing digital template, followed by embedding facial signature's digital template into the design in the form of secret biometric constraints, thereby generating a secured hardware accelerator design. The results report the following qualitative and quantitative analysis of the proposed biometric fingerprint approach: 1) impact of five different facial biometrics constraints on probability of coincidence (Pc) metric (indicating strength of digital evidence). The proposed approach achieves a very low Pc value in the range of 1.54E-5 to 2.01E-5; 2) impact of different facial feature set of a facial biometric image on total number of generated secret constraints and Pc. As evident, for all facial feature sets implemented, Pc ranges between 3.31E-4 and 2.01E-5; and 3) comparative analysis of proposed approach with recent work, for different DSP applications and five different facial biometric images, in terms of Pc. As evident, the proposed approach achieves significantly lower Pc, compared with recent work.

This article presents a novel methodology to secure hardware accelerators (such as digital signal processing (DSP) and multimedia intellectual property (IP) cores) against ownership threats/IP piracy using biometric fingerprinting. In this approach, an IP vendor's biometric fingerprint is first converted into a corresponding digital template, followed by embedding fingerprint's digital template into the design in the form of secret biometric constraints; thereby generating a secured hardware accelerator design. The results report the following qualitative and quantitative analysis of the proposed biometric fingerprint approach: 1) impact of 11 different fingerprints on probability of coincidence (Pc) metric. As evident, the proposed approach achieves a very low Pc value in the range of 2.22E-3 to 4.35E-6. Further, the biometric fingerprint achieves total constraints size between minimum 350 bits to maximum 895 bits; 2) impact of six different resource constraints on the design cost overhead of JPEG compression hardware postembedding biometric fingerprint. As evident, for all the resource constraints implemented, the design cost overhead is 0%; and 3) comparative analysis of proposed biometric fingerprint with recent work, for five different signature strength values, in terms of Pc. As evident, the proposed approach achieves minimum 3.9E+2 times and maximum 6.9E+4 times lower Pc, when compared to recent work.

Intellectual property (IP) cores used in consumer electronics devices mandate protection against reverse engineering (RE) attacks. Functional obfuscation protects the design functionality by enhancing the complexity of RE attacks. This paper proposes a novel low cost (based on power-delay tradeoff) functional obfuscation methodology through employment of robust IP locking technique. In the proposed obfuscation methodology, several strong multipairwise secure IP locking block designs are presented that can only be actuated through application of valid serial key bits. As demonstration, this paper also shows a practical example of a functional obfuscated netlist structure of FIR filter. Proposed obfuscation on comparison with a recent approach for several DSP cores yielded a power reduction of ~10%, design cost reduction ~ 6.5% and security enhancement (strength of obfuscation) of $>\,\,4.29\,\,{e+9}$ times.

I. VLSI Systems: A Glance Into The Last Decades Since their inception in 1970s, VLSI systems have enabled several new technological capabilities and made them accessible to an unceasingly wider range of users, reaching a scale that has been exponentially increasing over the decades[1](seeFig. 1). Relentless integration of more complex systems has driven such remarkable evolution, as made possible by the inexorable miniaturization. As shown inFig. 1, more functionality has been crammed in a consistently smaller form factor, as exemplified by the physical volume shrinking of computers by 100 X/decade[2],[3]. At the same time, the energy per task has been decreasing at 10–100 X/decade, as shown inFig. 2, for several systems and system-on-chip subsystems[4]. This allowed packing more capabilities into the same power envelope, as generally observed in the electronic systems, even before the advent of the integrated circuit[5].

Reusable intellectual property (IP) cores used in the consumer electronic devices, representing years of valuable investment, need protection against threats such as piracy and illegal claim of ownership. This paper introduces a novel 7-variable signature encoding driven triple-phase watermarking methodology during high level synthesis (HLS)/architectural synthesis for IP core protection of vendor rights. The proposed approach is extremely robust against external threats as it involves vendor signature comprising of 7-variable combination embedded through three independent phases of HLS. This paper is the first work in the HLS literature that presents a triple-phase watermarking process during HLS compared to single phase watermarking techniques so far. The proposed approach incurs zero delay overhead and minimal hardware overhead while embedding as well as yields average cost reductions of 7.38% and 6.25% compared to two similar approaches. Further, the proposed triple-phase watermark approach achieves a lower Pc value by ~3.2× 1027times in magnitude compared to similar approaches. Additionally, the proposed approach is 3.4 ×1043and 2.8 ×1019times more tamper tolerant than similar approaches.

Security against hardware Trojan that is capable to change the computational output value is accomplished by employing dual modular redundant (DMR) schedule during high level synthesis (HLS). However, building a DMR for Trojan security is nontrivial and incurs extra delay and hardware. This paper proposes a novel HLS methodology for constraint driven low cost hardware Trojan secured DMR schedule design for loop-based control data flow graphs (CDFGs). Proposed approach simultaneously explores an optimal schedule and optimal loop unrolling factor (U) combination for a low cost Trojan security aware DMR schedule. As a specific example, proposed low cost Trojan secured HLS approach relies on particle swarm optimization algorithm to explore optimized Trojan secured schedule with optimal unrolling that provides security against specific Trojan (causing change in computational output) within user provided area and delay constraints. The novel contributions of this paper are, first an exploration of a low cost Trojan security aware HLS solution for loop-based CDFGs; second, proposed encoding scheme for representing design solution comprising candidate schedule resources, candidate loop unrolling factor and candidate vendor allocation information; third, a process for exploring the a low cost vendor assignment that provides Trojan security; finally, experimental results over the standard benchmark that indicates an average reduction in final cost of ~12% compared to recent approach.

It is well understood that for Internet of Things (IoT), security of underlying hardware is the key to safe and reliable operation. IoT service stack relies on security of network, software, and firmware, all of which, in turn, depend on functionality provided by the underlying hardware. The hardware may be compromised or attacked by multiple threat actors. The designer may create a backdoor that leaks vital information such as encryption key used in secure channel; the manufacturer may tamper the design by inserting hardware Trojans or introducing artifacts with known reliability vulnerabilities. Either of these actors may enable writing into protected memory areas that may store secure hash of trusted code base, allowing malware to boot directly on the hardware. Today’s designs integrate IP blocks from multiple vendors; manufactured, tested, and repaired by different companies spanning across the globe. Consequently, there are many entry points for the hardware to be compromised. For a trusted hardware design, protection and security of intellectual property cores are of paramount importance. This special section aims to publish novel solutions for security problems related to hardware used in IoT.•Secured IoT Hardware: Induction of any form of third-party intervention in the hardware design methodology may raise grave security concern for IoT hardware. Securing IoT hardware can be in the form of protecting intellectual property cores against false claim of ownership/piracy/counterfeit. The first form of security measure requires anti-piracy methodologies such as digital watermarking, hardware metering, computational forensic engineering, and obfuscation that can nullify the false claim of ownership or detect unauthorized pirated designs. The second form of threat, which is formally called “hardware Trojan,” is an act of deliberate insertion into a design (such as intellectual property core, hardware) by a rogue designer or vendor, and also requires detection/correction strategies as a security measure. Both hardware threats discussed above may occur in any of the design abstraction levels (behavioral, register transfer, layout, etc.). Handling the threats higher in the abstraction level provides more assurance against possible attacks, however, it requires a more sophisticated approach. Further more, the level at which protective measure is applied often dictates the preprocessing or postprocessing style of the approach. These calls for novel technique that embeds hardware security measure a higher abstraction level for protection of IoT devices.•Reliable IoT Hardware: Due to multiple factors affecting reliability of hardware used in IoT devices, these devices are always at a risk of malfunctioning. For example, a manufacturer may deliberately change the width of a metal line for causing premature electromigration defect, possibly triggering a timed Trojan. Multiple trigger mechanisms may be used to attack hardware such as: 1) reducing device dimensions; 2) scaling supply voltage; and 3) modulating frequency of operation. Methodologies should incorporate techniques that provide resiliency/tolerance against such faults at higher abstraction levels to assure greater reliability from the beginning of design flow.•Low-Cost IoT Hardware:Another design aspect of hardware for IoT devices is performance and power. Consumer demand drives integration of multiple functionalities, often achieved by integrating dedicated IP cores and general purpose processors working in tandem. This creates a unique challenge in maintaining security and integrity of data passing through various IP blocks. Standard solutions involving redundancy, diversity, and check run up against power, performance, and latency constraints.

Intellectual property (IP) cores have emerged as a promising solution to the challenges of future design as well as mounting time to market pressure. However, due to increasing globalization of design supply chain, possibility of intervention and typical attacks is on the rise, which therefore mandates protection of IP cores from piracy/counterfeiting even at behavioral level. This paper presents a technique for generating low cost watermarking solution during high level synthesis (HLS) based on multi-variable signature encoding for security of reusable IP cores. The watermark generated by the proposed approach satisfies the following properties: (a) low embedding cost (b) robustness (c) low watermark creation time (d) strong proof of authorship (e) lower hardware overhead. Comparison with similar technique revealed that proposed approach obtains watermarked solution with lower embedding cost with less storage overhead and creation time.

An evolutionary algorithm (EA) driven novel design space exploration (DSE) of an optimized hardware Trojan secured datapath based on user power-delay constraint during high level synthesis (HLS) is presented. The focus on hardware Trojan secured datapath generation during HLS has been very little with absolutely zero effort so far in design space exploration of a user multi-objective (MO) constraint optimized hardware Trojan secured datapath. This problem mandates attention as producing a Trojan secured datapath is not inconsequential. Merely the detection process of Trojan is not as straightforward as concurrent error detection (CED) of transient faults as it involves the concept of multiple third party intellectual property (3PIP) vendors to facilitate detection, let aside the exploration process of a user optimized Trojan secured datapath based on MO constraints. The proposed DSE for hardware Trojan detection includes novel problem encoding technique that enables exploration of efficient distinct vendor allocation as well as enables exploration of an optimized Trojan secured datapath structure. The exploration backbone for the proposed approach is bacterial foraging optimization algorithm (BFOA) which is known for its adaptive feature (tumbling/swimming) and simplified model. Results of comparison with recent approach indicated an average improvement in quality of results (QoR) of >14.1%

A novel application of bacterial foraging optimization algorithm (BFOA) in the area of design space exploration (DSE) of datapath in high level synthesis (HLS) is presented in this paper. The BFOA has been transformed into an adaptive automated DSE framework that is capable to handle tradeoffs between area-execution time during HLS. To the authors belief, no such application (or transformation) of BFOA into DSE exist in the literature. The key sub-contributions of the proposed approach can be classified as follows: i) Exploration drift using a novel chemotaxis algorithm ii) Diversity introduction in resource configuration using a novel dispersal algorithm iii) Performance analysis of proposed and related approaches on metrics such as generational distance, maximum pareto-optimal front error, spacing, spreading and weighted metric. Finally, results indicated an average improvement in Quality of Results (QoR) of ∼6% and reduction in exploration runtime of > 18% compared to three recent approaches based on PSO and GA.