Presents a new framework and its prototype implementation for the distributed simulation of a mixed-signal system where some parts are modeled by differential and algebraic equations (as in SPICE) and other parts are modeled by discrete events (as in VHDL or Verilog). The work is built on top of a general-purpose framework of parallel and distributed simulation that combines both conservative and optimistic synchronization methods to extract the maximum concurrency available in such mixed analog and digital systems. We demonstrate that the maximum speedup can be achieved with digital components using optimistic scheduling and with analog components using conservative scheduling. A technique to further increase the parallelism among simultaneous events without sacrificing the simulation accuracy is proposed, by using a coarser time grain for the internal step events of analog solvers. Experimental results demonstrate a 6.2/spl times/ speedup on eight processors for a circuit described in VHDL and SPICE. This paper details our implementation, including how to make the numerical integration used by analog electrical-level event-driven simulation and to synchronize it with digital behavioral and gate-level simulation, analog/digital conversions, and how to resolve the non-convergence arising from straightforward analog and digital simulator integration. This paper also shows that optimistic synchronization for distributed analog simulation is feasible and quite efficient for small-to-medium-size analog blocks.

This paper presents a methodology for parallel and distributed simulation of VHDL using the PDES (parallel discrete-event simulation) paradigm. To achieve better features and performance, some PDES protocols assume that simultaneous events may be processed in arbitrary order. We describe a solution of how to apply these algorithms to have a correct simulation of the distributed VHDL cycle, including the delta cycle. The solution is based on tie-breaking the simultaneous events using Lamport's logical clocks to causally order them according to the VHDL simulation cycle, and defining the VHDL virtual time as a pair of simulation physical time and cycle/phase logical time. The paper also shows how to use this method with a PDES protocol that relaxes the simulation of simultaneous events to arbitrary order; allowing the LPs to self-adapt to optimistic or conservative mode, without the lookahead requirement. The lookahead is application-dependent and for some systems may be zero or unknown. The parallel simulation of VHDL designs ranging from 5531 to 14704 LPs using these methods obtained a promising, almost linear speedup.

This paper presents a new method for determining the widths of the power and ground routes in integrated circuits so that the area required by the routes is minimized subject to the reliability constraints. The basic idea is to transform the resulting constrained nonlinear programming problem into a sequence of linear programs. Theoretically, we show that the sequence of linear programs always converges to the optimum solution of the relaxed convex problem. Experimental results demonstrate that the sequence-of-linear-programming method is orders of magnitude faster than the best-known method based on conjugate gradients, with constantly better optimization solutions.

The paper presents a novel protocol for parallel and distributed simulation of VLSI systems. It is novel in two aspects: first, it combines optimistic and conservative synchronization methods, allowing processes to self-adapt for maximal utilization of concurrency. Second, it does not require any application-dependent information like lookahead, which in many cases is unknown, zero, or difficult to automatically obtain from a design in a hardware description language. All these features make it very convenient and practical, extending the class of applications to at least all VHDL circuits, including delta cycle. The proposed protocol has been implemented and used for VHDL simulation. Experimental results on several large VHDL circuits (between 1411 and 14704 processes) have shown promising linear speedups. We also observed that the dynamic synchronization, in which processes automatically adapt to optimistic or conservative behavior, follows closely or finds a very good configuration. This protocol may have a strong impact for mixed-signal circuit simulation, where digital parts may be optimistic and heavy-state analog parts, conservative.