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Marinés Puig-Medina

dblp:37/3299 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2000
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 91% Processor architecture and microarchitecture · 9%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
coverage analysis
0.012000
Verification of configurable processor cores · DAC 2000
Electronic design automation
hardware verification and test
0.012000
Verification of configurable processor cores · DAC 2000
Electronic design automation › hardware verification and test
processor verification
0.012000
Verification of configurable processor cores · DAC 2000

Methods — techniques the papers use, named apart from their topics

simulation-based verification · 0.0pseudo-random program generation · 0.0directed diagnostics · 0.0
YearPublicationVenuePosition
2000 Verification of configurable processor cores
abstract
This paper presents a verification methodology for configurable processor cores. The simulation-based approach uses directed diagnostics and pseudo-random program generators both of which are tailored to specific processor instances. A configurable and extensible test-bench serves as the framework for the verification process and offers components necessary for the complete SOC verification. Coverage analysis provides an evaluation of how well a specific design has been exercised, of the breadth of the configuration space explored, and suggests improvements to the process. The results of the analysis show that our methodology achieves good verification coverage of the processor implementation.
Marinés Puig-Medina, Gülbin Ezer, Pavlos Konas
DAC1