In recent years, various obfuscation techniques have been proposed to protect analog circuits against IP piracy attacks. To evaluate the strength of the analog obfuscation techniques, attack algorithms including the equation-based SMT attack, genetic algorithm, key spacing attack, and monotonic response algorithm have been proposed. However, unlike the digital domain, where the SAT attack is the de-facto standard for measuring the resiliency of the key-based locking techniques, no standard metric exists to evaluate analog obfuscation techniques. In this article, a novel DC nodal analysis (DNA) attack algorithm is proposed that requires only the circuit netlist and the large signal DC input-output response of an oracle IC. The DNA attack utilizes Kirchhoff’s voltage law (KVL) and Kirchhoff’s current law (KCL) to efficiently explore the obfuscated parameter space of an analog circuit and determine the correct control parameters that result in a circuit response similar to that of the oracle IC. The proposed attack is evaluated against four distinct analog circuits secured using key-based parameter obfuscation and multi-threshold obfuscation. The results from execution of the attack on a three stage front-end circuit secured with the key-based obfuscation technique indicate the successful elimination of 99.1% of keys from the search space in less than five days. The results from evaluating the attack on the same three stage front-end circuit secured with the multi-threshold obfuscation technique indicate the successful elimination of 99.98% of keys from the search space in 50.4 hours. With the limited information necessary to perform the attack, the efficiency in pruning the key-space when considering real world attack scenarios, and the ability to execute the attack across all current analog locking techniques, the DC nodal analysis attack provides a de-facto standard to measure the security provided by an analog obfuscation technique.

The growing complexity and performance demands of modern computing systems resulted in a shift from traditional System-on-Chip (SoC) designs to Network-on-Chip (NoC) architectures, and further to three-dimensional Network-on-Chip (3D NoC) solutions. Despite their performance and power efficiency, the increased complexity and inter-layer communication of 3D NoCs can create opportunities for adversaries who opt to prevent reliable communications between embedded nodes by inserting hardware Trojans in such nodes. The hardware Trojans, introduced through untrusted third-party Intellectual Property (IP) blocks, can severely compromise 3D NoCs by tampering with data integrity, misrouting packets, or dropping them; thus triggering denial-of-service attacks. Detecting such behaviors is particularly difficult due to their infrequent activation. Thereby it is of utmost importance to take the trustworthiness of the embedded nodes into account when routing the packets in the NoCs. Accordingly, this paper proposes a trust-aware routing scheme, so-called TARN, to significantly reduce the rate of packet loss that can occur due to malicious behaviors of one or more nodes (or interconnects). Our distributed trust-aware path selection protocol bypasses malicious IPs and securely routes packets to their destination. Furthermore, we introduce a low-overhead mechanism for delegating trust scores to neighboring routers, thereby enhancing network efficiency. Experimental results demonstrate significant improvements in packet loss while imposing low performance and energy overhead.

Representation learning has become an effective technique utilized by electronic design automation (EDA) algorithms. By addressing challenges related to the increasing complexity of circuits and the corresponding stringent power, performance, and area (PPA) requirements, representation learning facilitates the automatic extraction of meaningful features from complex data formats, including images, grids, and graphs. In this paper, the application of representation learning to digital IC design automation is explored with an analysis of prior work on foundational concepts and case studies on tasks that include timing prediction and routability analysis. Key techniques, including image-based methods, graph-based approaches, and hybrid multimodal solutions, are described that highlight the improvements provided in routing and timing prediction. The provided advancements demonstrate the potential of representation learning to enhance efficiency, accuracy, and scalability in current integrated circuit design flows.

A model that utilizes a graph neural network (GNN) is proposed to estimate wirelength in the early stages of physical design. The model predicts the post-routing wirelength of a net, which addresses the limitations of current estimators including half-perimeter wirelength (HPWL) that tend to under-estimate the true post-routed wirelength of complex nets. Utilizing a dataset of 18 benchmark circuits, the GNN achieves an average R2of 0.825, outperforming HPWL, which yields an R2of 0.764. The GNN demonstrates consistent performance across nets of varying lengths, providing significantly improved accuracy over HPWL for long and multi-path nets. The GNN model is differentiable and compatible with gradient-based optimization methods, while providing an 8× improvement in inference time.

In this article, a novel field-programmable analog array (FPAA) has been developed for the configurable implementation of various analog circuits. The proposed architecture not only supports system-level reconfiguration but also enables transistor-level programmability. The FPAA is comprised of a$3\times 4$configurable analog block (CAB) array, with a single configurable logic block (CLB) added to each column to allow for the programming of digital circuits. Passive devices, including programmable capacitors and resistors, and active transistor pairs (TPs), are utilized to implement both continuous-time and discrete-time circuits. A placement algorithm is developed that efficiently maps analog circuits onto the FPAA fabric by finding the optimal vertical and horizontal locations for the assignment of transistors. In addition, to reduce the complexity of placing devices on the fabric, a technique is developed that matches TPs in the same vertical level to predefined topologies in a library. Routers are included to connect devices implemented on the FPAA fabric. The proposed FPAA occupies an area of 4 mm2in a TSMC 65-nm fabrication process. The smaller circuits implemented on the FPAA fabric include a folded-cascode amplifier, a strongArm comparator, a continuous-time integrator, and a switch-capacitor integrator. The larger analog and mixed-signal circuits implemented on the FPAA fabric include a four-stage pipeline analog-to-digital converter (ADC) and a first-order delta-sigma modulator. The programmed folded-cascode amplifier exhibits a tunable gain of 28.3 dB to 34.8 dB and a programmable 3-dB bandwidth of 3.3 MHz to 5.3 MHz. The configured comparator provides a resolution of less than 3 mV when comparing two signals. The implemented first-order delta-sigma modulator operates at a frequency of 15 MHz and provides an effective number of bits (ENOBs) of 6.8 when utilizing an oversampling ratio of$128\times $. The configured pipeline ADC provides an ENOB of 3.7 for a sampling frequency of 15 MHz.

As 3-D integrated circuits (ICs) increasingly pervade the microelectronics industry, the integration of heterogeneous components presents a unique challenge from a security perspective. To this end, an attack on a victim die of a multi-tiered heterogeneous 3-D IC is proposed and evaluated. By utilizing on-chip inductive circuits and transistors with low voltage threshold (LVT), a die based on CMOS technology is proposed that includes a sensor to monitor the electromagnetic (EM) emissions from the normal function of a victim die, without requiring physical probing. The adversarial circuit is self-powered through the use of thermocouples that supply the generated current to circuits that sense EM emissions. Therefore, the integration of disparate technologies in a single 3-D circuit allows for a stealthy, wireless, and non-invasive side-channel attack. A thin-film thermo-electric generator (TEG) is developed that produces a 115 mV voltage source, which is amplified 5 × through a voltage booster to provide power to the adversarial circuit. An on-chip inductor is also developed as a component of a sensing array, which detects changes to the magnetic field induced by the computational activity of the victim die. In addition, the challenges associated with detecting and mitigating such attacks are discussed, highlighting the limitations of existing security mechanisms in addressing the multifaceted nature of vulnerabilities due to the heterogeneity of 3-D ICs.

The growing complexity of very large-scale integrated (VLSI) circuits due to CMOS technology scaling has led to an increased interest in utilizing machine learning (ML) techniques for design automation. However, the lack of available datasets and established standards for the representation of datasets presents substantial challenges within the research community. Of particular concern is the lack of interoperability and comparability of ML-driven research in the design of digital circuits, which effectively limits collaboration. In this paper, EDA-schema, an open and comprehensive graph schema, is introduced to address such challenges by providing a structured framework for representing datasets for digital design automation. The schema represents the physical attributes and quality-of-results (QoR) metrics of a circuit across various stages of the physical design flow, including logical synthesis, floorplanning, placement, clock network synthesis, and global and local routing. Utilizing the Skywater 130 nm process design kit (PDK) and the OpenROAD toolset, a dataset of physical designs is generated and analyzed based on the circuits from the IWLS’05 benchmark suite. The dataset is made publicly available, anticipating contributions that further advance the field of ML-driven digital design.

In this paper, novel block configuration algorithms are developed for a field-programmable analog array (FPAA). The proposed architecture and algorithms not only support system-level reconfiguration but also allow for transistor-level programmability. Programmable capacitors, resistors, and transistor pairs are utilized to facilitate both continuous-time and discrete-time signal processing. A placement algorithm is proposed to efficiently map an analog circuit onto the FPAA fabric by determining the optimal vertical and horizontal locations for the assignment of transistors. The FPAA contains a 3x4 configurable analog block (CAB) array, with a configurable logic block (CLB) added to each column for digital circuit programmability. The proposed FPAA occupies an area of 4 mm2in a 65 nm process. The circuits implemented on the FPAA fabric include a folded-cascode amplifier, a switch-capacitor integrator, and a first-order delta-sigma modulator. The reconfigured folded-cascode amplifier exhibits a gain of 32 dB with a 3-dB bandwidth of 30 MHz, while the implemented integrator and delta-sigma modulator operate at a frequency of 15 MHz.

Algorithms have been proposed to evaluate the resiliency of analog obfuscation techniques. Each analog deobfuscation algorithm considers different threat models, applies to only a small set of obfuscation techniques, and suffers adversely under real world scenarios, where one or more pieces of information on the circuit and obfuscation technique or techniques is unavailable to the attacker. In this paper, a novel DC nodal analysis (DNA) attack algorithm is proposed that requires only the circuit netlist and the DC input-output response of the oracle IC to perform the attack. The DNA attack utilizes Kirchhoff’s voltage law (KVL) and Kirchhoff’s current law (KCL) to efficiently characterize an obfuscated analog circuit with the objective of determining the correct locked parameters. A preliminary evaluation of the proposed attack is performed on three distinct analog circuits secured using both key-based parameter obfuscation and non-key-based multi-threshold obfuscation. The results from executing the attack on a secured single-stage analog circuit with key-based obfuscation indicate the successful elimination of, on average, 96% of keys from the search space. The results from executing the attack on two-stage circuits secured with multi-threshold obfuscation indicate that 99.58% of the keys are eliminated in less than 7 hours. With the limited information necessary to perform the attack, the efficiency in pruning the key-space when considering real attack scenarios, and the application of the attack to all current analog obfuscation techniques, the DNA attack provides the de-facto standard in the characterization of the resiliency of an analog obfuscated circuit.

With technology scaling, interconnect impedance becomes a dominant factor that affects the performance of integrated circuits. Estimating the interconnect impedance of analog circuits at early design stages has been a persistent challenge, primarily due to the lack of detailed layout information. Even with accurate parasitic extraction after routing, many iterations of modifications to the design are required to compensate for the effects of interconnect impedance. To address this challenge, a novel approach is proposed in this work that leverages graph neural networks (GNNs) for the estimation of the interconnect capacitance of an analog circuit at both the schematic and post-placement stages of the design flow. A device-level circuit is represented as a heterogeneous graph, where two node types are utilized, one representing transistors and the other representing nets. The GNN model, specifically, the relational GraphSAGE network, is applied to update the embeddings of net nodes, which are then used to predict the lumped capacitance of a net. To allow the model to learn the spatial relationships between devices after placement, the pairwise Manhattan distances between devices are utilized as edge weights during the aggregation of node embeddings. A dataset of ten analog circuits is utilized to evaluate the proposed model. The developed GNN model for post-placement prediction of capacitance that utilizes pairwise Manhattan distances results in an R2score of 0.73 and a mean absolute error of 0.26 fF, outperforming both the schematic-level prediction model and the post-placement prediction model that directly utilizes device coordinates as features. Results confirm that the proposed model effectively estimates the interconnect capacitance of analog circuits at early design stages while requiring a small dataset for training.

In this paper, a monotonic power side-channel attack (PSA) is proposed to analyze the security vulnerabilities of flash analog-to-digital converters (ADC), where the digital output of a flash ADC is determined by characterizing the monotonic relationship between the traces of the power consumed and the applied input signals. A novel technique that leverages clock phase division is proposed to secure the power side channel information of a 4-bit flash ADC. The proposed technique adds randomness to decorrelate the input signal from the given power trace as the execution phase of each comparator depends on a thermometer code computed from the previous seven clock cycles. The monotonic PSA is executed on both a secured and unsecured ADC, with results indicating 1.9 bits of information leakage from an unprotected ADC and no data leakage from a protected ADC as the bit-wise accuracy is approximately 50% when secured. The monotonic PSA is more effective at attacking a flash ADC architecture than either a convolutional neural network based PSA or a correlation template PSA. The secured ADC core occupies approximately 2% more area than a non-secure ADC in a 65 nm process, and provides a sampling frequency of up to 500 MHz at a supply voltage of 1.2 V.

An accurate early estimate of the post routing inter-connect parasitics allows for pre-emptive changes to the circuit in earlier phases of the design flow, significantly reducing the design time and effort. In this work, graph based deep regression models are proposed to predict the post routing interconnect capacitance of a circuit by utilizing layout information and the post placement estimates of the interconnect parasitics. The post placement capacitance determined by a commercial physical design tool is used as a baseline for the models, with the mean absolute percentage error (MAPE), the mean absolute error (MAE), and$R^{2}$score calculated for comparison. The proposed methodology outperforms the baseline provided by the commercial physical design tools based on results obtained across all trained models, with an average improvement of 23.39% in MAPE, 5.33% in MAE, and 1% in$R^{2}$score. The proposed methodology also provides better prediction of the worse case errors as compared to the commercial tool, with the model providing an average improvement of 47.43% in MAPE and 14.31 % in MAE for the nets with the largest 1 % of errors as determined by the tool.

Recently, graph neural networks (GNNs) have been applied to various circuit applications, where circuit topology is leveraged in the learning of the models. However, the aggregation of GNN models has not accounted for circuit hierarchies. In addition, the generalization of GNNs to distinguish between different circuit topologies is not currently provided, which raises the question of whether one GNN is sufficient to simultaneously model differing circuit graphs. In this work, a graph representation is proposed, based on a given circuit netlist, to model analog circuits at the transistor level. Additional categorical features are included to address the ambiguity in modeling the connections of the terminals of a given transistor. Edge-conditioned convolution (ECC) is utilized, where weight matrices conditioned on the edge attributes are trained in the local neighborhood of a given node. A relational graph is constructed to model groupings of devices for each level of the hierarchy provided by the designer. Each adjacency matrix of the relational graph is processed by a graph isomorphism network (GIN) layer, described as a Circuit-GIN layer, to update the node embeddings. The model consisting of an ECC layer and two Circuit-GIN layers, described as a Circuit-GNN, is trained on data from four op-amp topologies to predict four performance parameters. Results indicate that the ECC-based model outperforms a GCN-based model in the prediction of all of the performance parameters, which results from the additional edge information learned by the ECC layer. With the addition of Circuit-GIN layers, the Circuit-GNN outperforms the ECC-only model by up to 16.7% in$\boldsymbol{R}^{\mathbf{2}}$score. Therefore, aggregation of node embeddings based on device groupings brings additional benefit to guide the GNNs in modeling the performance of analog ICs. The work also validates the expressive power of the proposed GNN model, which generates embeddings that distinguish between different circuit graphs. The generalization of GNNs renders feasible the simultaneous learning from different analog topologies.

Analog obfuscation techniques to prevent intellectual property attacks have mainly evolved from digital obfuscation. Similar to digital hardware security, the considered threat models commonly assume that the attacker possesses the circuit netlist, specifications, and bias information to deobfuscate a locked analog circuit. However, when one or more pieces of information remain unavailable, there is an adverse effect on the performance of current analog attack algorithms. In this article, an analysis of the challenges and limitations of obtaining the information needed to successfully attack an analog circuit is provided. In addition, the performance of current state-of-the-art analog attack techniques is evaluated when one or more pieces of information is unavailable. The analysis of the attack on five distinct analog circuits obfuscated with key-based parameter locking is performed, premised upon the level of information possessed by the adversary. The monotonic attack (MA) returned the correct key in less than 10 h when executing a black-box attack on single stage circuits obfuscated with a 10-bit key. The key-spacing (KS) attack is$10\times $faster than the monotonic attack and returns$8.3\times $fewer candidate keys for multistage analog circuits. The satisfiability modulo theory (SMT) based attack is$224\times $slower than the monotonic attack and$2240\times $slower than the key spacing attack for an 18-bit obfuscated circuit. A genetic algorithm (GA) based attack is 121$091\times $slower than an monotonic attack even for a single stage analog circuit. Through analysis of the results, metrics are developed to characterize the setup and evaluation time of executing the deobfuscation attacks.

This paper presents RAPTA, a customized Representation-learning Architecture for automation of feature engineering and predicting the result of Path-based Timing-Analysis early in the physical design cycle. RAPTA offers multiple advantages compared to prior work: 1) It has superior accuracy with errors std ranges 3.9ps~16.05ps in 32nm technology. 2) RAPTA's architecture does not change with feature-set size, 3) RAPTA does not require manual input feature engineering. To the best of our knowledge, this is the first work, in which Bidirectional Long Short-Term Memory (Bi-LSTM) representation learning is used to digest raw information for feature engineering, where generation of latent features and Multilayer Perceptron (MLP) based regression for timing prediction can be trained end-to-end.

In this paper, a novel field-programmable analog array (FPAA) is proposed to secure the intellectual property (IP) of analog and mixed-signal circuits. A obfuscation technique is developed to efficiently mask the topology of both differential mode and single-ended mode analog circuits. The overhead in performance due to the parasitic impedance of the routing switches is analyzed at the internal nodes connected to the programming switches. Advantages of topology obfuscation include the generation of a large search space, an uncorrelated output response, and flexibility in circuit design. The circuits implemented on the FPAA include an op amp with varying loads, a second order biquad filter, a ring-oscillator, and a frequency divider. For circuits requiring a single configurable analog block (CAB) on the FPAA, the 3 dB bandwidth is maintained around 1 GHz, while circuits requiring multiple CABs operate with frequencies between 200 MHz and 1.5 GHz. The security provided by the FPAA fabric is evaluated on both single CAB implementations as well as multi-CAB circuits. Two attack scenarios are considered, a brute force attack and a topology attack. The multi-CAB circuit provides strong security robustness to both attacks with a minimum search space of 226for the brute force attack and 210for the topology attack. The FPAA core is implemented in a 65 nm process with an area of 0.1 mm2.

Oracle guided attacks, such as the SAT attack, and finite state machine (FSM) reconstruction-based structural attacks are two primary threats to sequential logic obfuscation of an integrated circuit (IC). Recent defense mechanisms apply hidden state transitions (HST) and logic cone modifications to a partitioned FSM to protect against both oracle-guided and structural attacks. HST triggering techniques are implemented on select state registers to induce controlled timing glitches in the FSM. However, the current implementations of HST are vulnerable to structural attack through the gate-level logic implementing the trigger. In this paper, a random walk-based security estimation metric is utilized to quantify the security of gate-level masking of the triggering topology. A novel coupling capacitance-based HST triggering topology is proposed, where the glitch is induced by manipulating the physical properties of the circuit rather than the gate-level logic. An average increase of 8.53$\times$ in the random walk-based security estimation score and an 887x increase in the geometric mean of the expected number paths to extract the key is observed for coupling capacitance based HSTs as compared to traditionally triggered HSTs. The schematic level equivalent of the proposed technique is implemented on a subset of ISCAS’89 benchmark circuits, resulting in an average overhead in area and power of 14.35% and 22.02% for all benchmark circuits and 2.23% and 1.25% for the four largest benchmark circuits, respectively, as compared to the original unobfuscated circuits.

A transfer learning technique is proposed that utilizes models trained on data in one technology node to predict the performance of a circuit based on the sizing of transistors in another technology node. Specifically, neural networks optimally trained on data from the source technology node are adopted as pre-trained models. During transfer training, the front layers of the pre-trained models are frozen while the remaining layers are re-trained with significantly less data in the target technology node. The transfer learning technique is applied to the prediction of seven performance metrics of an operational amplifier based on seven design variables that include the sizing of transistors and capacitors. Models trained on a dataset containing 1602 simulated design points from a 180 nm process are transferred to predict the performance metrics of the op-amp utilizing only 100 simulated design points from a 65 nm process. During the training of the transferred models, the learning curve exhibits an improved starting point and a lower asymptotic error. Utilizing the same training set of 100 points from the 65 nm process, applying transfer learning reduces the normalized mean average error (MAE) on the test (inference) set in all cases by up to 50% as compared to training standalone models. For the transferred models, a detailed characterization of the test error as a function of the number of frozen layers is performed. Results indicate that the transferred gain predictor trained with only 100 data points provides a lower test error than the standalone model trained with 1000 data points without transfer learning in a 65 nm process. Therefore, transfer learning improves the sample efficiency of the training of the neural networks used for the prediction of the performance parameters of a circuit, which provides benefit for design migration when the collection of new circuit data is computationally costly in the target process node.

This paper purposes a Reinforcement Learning solution for peak current reduction by clock skew engineering. The reinforcement learning agent learns how to adjust each register's clock arrival time to maximize the clock arrival's distribution. The use of reinforcement learning allows us to explore optimization opportunities in clock tree synthesis beyond the heuristic algorithms used in modern EDA tools. Our experimental results support this claim as we report over 35% drop in peak current and major reduction in IR drop (from package to transistor) in the selected benchmarks. The agent explores despite creating timing violations and receives a large negative reward for its action. The agent, however, can receive a bonus reward in the future if the timing violation was fixed later by adjusting the clock arrival time of other registers, resulting in a broader spread in clock arrival distribution.

With the recent introduction of techniques to restrict scan chain access, a new class of deobfuscation problems emerge, in which the threat model, although similar to deobfuscation of a logic locked circuit, forms a novel class of attack. In this paper, the concept of a logic restricted circuit is generalized and defined. Next, a novel type of SAT-based attack is proposed for the new class of deobfuscation problems, described as a 2-stage SAT-attack. A SAT-attack resilience measure is developed to quantify the security strength of a logic restricted circuit against a SAT-based attack. Finally, the proposed SAT-resilience framework is applied to compare and evaluate effectiveness of example logic restriction schemes.

In this paper, a novel field-programmable analog array (FPAA) fabric consisting of a 6x6 matrix of configurable analog blocks (CABs) is proposed. The implementation of programmable CABs eliminates the use of fixed analog sub-circuits. A unique routing strategy is developed within the CAB units that supports both differential and single-ended mode circuit configurations. The bandwidth limitation due to the routing switches of each individual CAB unit is compensated for through the use of a switch-less routing network between CABs. Algorithms and methodologies are developed to facilitate rapid implementation of analog circuits on the FPAA. The proposed FPAA fabric provides high operating speeds as compared to existing FPAA topologies, while providing greater configuration in the CAB units as compared to switch-less FPAAs. The FPAA core includes 498 programming switches and 14 global switchless interconnects, while occupying an area of 0.1 mm2in a 65 nm CMOS process. The characteristic power consumption is approximately 24.6 mW for a supply voltage of 1.2 V. Circuits implemented on the proposed FPAA fabric include operational amplifiers (op amps), filters, oscillators, and frequency dividers. The reconfigured bandpass filter provides a center frequency of approximately 1.5 GHz, while the synthesized ring-oscillator and frequency divider support operating frequencies of up to 500 MHz.

Oracle guided attacks, such as the satisfiability attack, are a significant concern when obfuscating an integrated circuit (IC). Partitioned finite state machine (FSM) based sequential logic locking techniques are much more resilient to oracle guided attacks due to the differences in the state space between the oracle and the IC under attack. However, susceptibility to structural attacks and the extraction of the transition state between the obfuscated and functional modes of an FSM threaten the efficacy of sequential logic locking. Therefore, a methodology to synthesize hidden state transitions (HSTs) into an FSM within an IC is developed. HSTs and logic cone modifications are utilized to further enhance the security of sequentially locked circuits by increasing the number of paths an adversary must search and reducing the susceptibility to structural attacks. An algorithm to insert hidden transitions and logic cone modifications into a netlist is developed that results in an average overhead of 6.79% in area, 7.78% in power, and 8.28% in performance across all of the ISCAS'89 sequential benchmark circuits. To modify the logic cone with two altered minterms, the average increase in area and power, beyond what is needed for the implementation of HSTs, is 26.46% and 30.30%, respectively, with no additional overhead in performance.

Current out-of-cone logic locking methodologies provide resilience against the satisfiability (SAT) attack with minimal corruption of the outputs when comparing an activated and locked integrated circuit (IC). In addition, the structure of the modifications to the original logic leaks functional information of the circuit, which allows an adversary to determine the correct key. A novel logic locking methodology, CORruption adaptable logic locking (CORALL), is introduced in this article that provides increased security against the SAT attack for modified logic cones that require a large corruption of the primary outputs of the circuit, where the corruption is quantified by comparing between an activated and locked state of the IC. In addition, the modifications to the logic cone utilized by CORALL provide increased resilience against structural attacks. The CORALL architecture increases the number of iterations required to successfully execute a SAT attack for a flip function with 20 inputs by 34.41× over SFLL-HD n/4 and 82.36× over SFLL-Flex. In addition, a protected-cube selection process based on iterative cofactors is introduced, which provides varying logical functions of the perturb unit and maps portions of the logic of the perturb unit into the look-up tables (LUTs) of the CORALL architecture. The variation in the logical functions implemented by the perturb unit and the mapped functionality of the perturb unit into a LUT provide resistance to all current structural attacks on out-of-cone logic locking techniques.

In this article, key-based obfuscation of the transistor dimensions is proposed to mask the biasing conditions of an analog circuit and, therefore, protect the circuit against intellectual property (IP) piracy. Vector- and mesh-based obfuscations are developed that provide different degrees of circuit security with tradeoffs in design complexity and area. An algorithm for the selection of an obfuscation transistor and a satisfiability modulo theory (SMT)-based algorithm that searches the design space to determine the dimensions of the obfuscation transistors are developed to reduce the computational complexity of designing and implementing the proposed parameter obfuscation techniques. The parameter obfuscation techniques, along with the developed algorithms, are implemented on an active inductor-based second-order bandpass filter (BPF) and an operational amplifier (op-amp). The results from the analysis of the obfuscated BPF and op-amp indicate that the critical circuit performances are properly locked with at least 15% variation from the target circuit parameters when setting incorrect transistor sizes. A simulation-based optimization algorithm is proposed to tune the biasing conditions and transistor body voltages, which mitigates the effects of both the parasitic impedance of the circuit and any variation due to the implementation of the obfuscation circuitry. The proposed simulation-based optimization algorithm determines the biasing conditions and body voltages of the BPF in 500 iterations and the op-amp circuit in 70 iterations, which provides a significant reduction in the design time and the number of circuit recycles. Implementing the parameter obfuscation technique with the proposed algorithms provides an efficient means to secure analog circuits while reducing the design time to implement security features.

A novel technique to secure the scan chain of an integrated circuit (IC) is proposed. The technique creates a logical partition between the functional and test modes of a circuit, where the correct logic locking key is only provided in functional mode. The proposed technique allows for the security of the logic cone through logic locking and secures the outputs of the circuit from the scan chain without modifications to the structure of the scan chain. Since the oracle responses in test mode do not correspond to the functional key, satisfiability (SAT) attacks are not able to leverage the responses from the scan chain. In addition, a charge accumulation circuit is developed to prevent and detect any attempt to enter the partitioned test mode while the correct circuit responses are still stored within the registers. The charge accumulation circuit results in a 9.2% increase in area as compared to a minimum sized 180 nm 2-input NAND gate. Implementing the technique on the ISCAS'89 s15850 benchmark circuit results in a 2.87% increase in the total area.

In this paper, a metric based on mathematical modeling is proposed to evaluate the strength in security of a logic-locked circuit against a satisfiability (SAT) based attack. Current approaches estimate the SAT resilience experimentally based on time-to-solve or the number of calls to a SAT-solver. However, the estimate is often based on one sample or a small sample size. Due to the possible variation in the search path length of the SAT-attack, a measure of resilience based on statistical characterization is proposed. A probabilistic model of a SAT-attack search process is developed to properly capture the variation in the path length and report the SAT resilience as an expectation of the computational complexity. An estimator of the expected complexity, assuming an equally likely branching probability, is proposed. The model and the estimator allow for 1) the derivation of a closed-form estimate of the expected security, and 2) characterization of the key search space without experimental bias toward SAT-attack implementation or circuit topology. As a case study, an analysis of the security gain per inserted key gate is performed on a full adder circuit. The study reveals a monotonically increasing resilience and provides insights on the most efficient key gate placement strategy that maximizes the achievable security.

Vulnerabilities of key based analog obfuscation methodologies that modify the transistor dimensions of a circuit are evaluated. Two attack vectors on a common source amplifier, differential amplifier, operational amplifier, and voltage controlled oscillator are developed. The first attack exploits the lack of possible key combinations permitted around the correct key, which is a result of requiring a unique key to lock the circuit. An average of 5 possible key combinations were returned in an average of 5.47 seconds when executing the key spacing attack. The second attack vector utilizes the monotonic relationship between the sizing of the transistors and the functional response of the circuit to determine the correct key. The average time to execute the attack, while assuming process, voltage, and temperature (PVT) variation of 10%, was 1.18 seconds. Both equal key spacing and non-monotonic key dependencies are discussed as ways to mitigate the threats to future analog obfuscation techniques.

In this paper, algorithmic and circuit techniques are proposed for dynamic power management that allows for the reuse of the leakage current of idle circuit blocks and cores in a multiprocessor system-on-chip platform. First, a novel scheduling algorithm, longest idle time - leakage reuse (LIT-LR), is proposed for energy efficient reuse of leakage current, which generates a supply voltage of 340 mV with less than ±3% variation across the tt, ff, and ss process corners. The LIT-LR algorithm reduces the energy consumption of the leakage control blocks and the peak power consumption by, respectively, 25% and 7.4% as compared to random assignment of idle cores for leakage reuse. Second, a novel usage ranking based algorithm, longest idle time - simultaneous leakage reuse and power gating (LIT-LRPG), is proposed for simultaneous implementation of power gating and leakage reuse. Applying power gating with leakage reuse reduces the total energy consumption of the MPSoC by 50.2%, 14.4%, and 5.7% as compared to, respectively, a baseline topology that includes neither leakage reuse or power gating, only includes power gating, and only includes leakage reuse.

The resiliency of in-cone logic locking techniques to the satisfiability (SAT) attack is characterized in this paper. An analysis of the parameters of the SAT solver that impact security and a characterization of the effect netlist topology has on the security of the circuit is presented. The analysis of SAT solver parameters and logic structure is used to develop three novel logic locking gate selection algorithms based on maximum fanout free cones (MFFCs) and gate controllability for circuits implementing XOR, look-up table (LUT), and 2× 1 MUX-based logic obfuscation. The XOR, LUT, and MUX MFFC-based algorithms resulted in an average increase of, respectively, 61.8%, 123.6%, and 38.5% in the minimum number of iterations required to complete the SAT attack across 1,000 different variable orderings of the netlist while applying the locking techniques to 5% of the gates within the netlist. In addition, the SAT attack resiliency and output corruption of the developed algorithms are compared with out-of-cone locking techniques.

The transition to a horizontal integrated circuit (IC) design flow has raised concerns regarding the security and protection of IC intellectual property (IP). Obfuscation of an IC has been explored as a potential methodology to protect IP in both the digital and analog domains in isolation. However, novel methods are required for analog mixed-signal circuits that both enhance the current disjoint implementations of analog and digital security measures and prevent an independent adversarial attack of each domain. This paper demonstrates the vulnerabilities of implementing disjointed obfuscation techniques to protect analog mixed-signal ICs. In addition, a novel methodology is developed to generate functional and behavioral dependencies between the analog and digital domains that results in an increase in the adversarial key search space. The dependencies between the analog and digital keys result in a 3x increase in the number of iterations required to complete the SAT attack. An analysis of best practices is also provided to aid in the implementation of security measures for analog mixed-signal circuits.

An on-chip power management technique is developed that makes use of particle swarm optimization (PSO) to improve the performance per watt of the circuit while maintaining the power integrity. On-line learning is applied to determine the optimum reference voltages of the on-chip voltage regulators set through the PSO to reduce the energy consumption of the system while preventing any timing failure due to process variation, voltage variation, temperature, and aging. The runtime adaptive voltage delivery technique is applicable to any processor architecture. Simulation results on a streaming multiprocessor similar to the NVIDIA GV100 GPU in a 7 nm FinFET technology indicate an average reduction of 35%, 40%, and 5% in, respectively, the power consumption, the threshold voltage drift, and the operating temperature as compared to existing techniques that implement static voltage guardbands.

A novel method for the delivery of power to subthreshold (sub-Vt) circuits is proposed. The unused leakage current during idle-mode operation of super-threshold (super-Vt) circuits is used to supply sub-Vtcircuits. Super-Vtand sub-Vtcircuits are simulated in a 45 nm CMOS technology, where the super-Vtcircuits operate at 1.2 V and generate a sub-Vtvoltage of 380 mV. The proposed technique is compared with two conventional methods, one that uses separate power distribution networks for super-Vtand sub-Vtcircuits (baseline) and the second that implements voltage stacking. The implementation of the proposed leakage reuse (LR) technique on the s27 ISCAS89 benchmark circuit results in a reduction of the total, static, and peak power consumption to, respectively, 0.41×, 0.207×, and 0.7× that of the baseline technique. The leakage reuse technique also reduces the peak voltage noise on VSSand the VSSsettling time to, respectively, 0.68× and 0.44× that of the baseline at a cost of a 1.24× increase in the FO4 delay. In addition, the LR technique implemented on the s208 ISCAS89 benchmark circuit reduces the peak voltage noise on the virtual ground (VGND) and the VGND settling time to, respectively, 0.28× and 0.23× that of the voltage stacking technique.

A method to increase the resiliency of in-cone logic locking against the SAT attack is described in this paper. Current logic locking techniques provide protection through the addition of circuitry outside of the original logic cone. While the additional circuitry provides provable security against the SAT attack, other attacks, such as the removal attack, limit the efficacy of such techniques. Traditional in-cone logic locking is not prone to removal attacks, but is less secure against the SAT attack. The focus of this paper is, therefore, the analysis of in-cone logic locking to increase the security against the SAT attack, which provides a comparison between in-cone techniques and newly developed methodologies. A novel algorithm is developed that utilizes maximum fanout free cones (MFFC). The application of the algorithm limits the fanout of incorrect key information. The MFFC based algorithm resulted in an average increase of 61.8% in the minimum number of iterations required to complete the SAT attack across 1,000 different variable orderings of the circuit netlist while restricted to a 5% overhead in area.

In this paper, a technique to design analog circuits with enhanced security is described. The proposed key based obfuscation technique uses a mesh topology to obfuscate the physical dimensions and the threshold voltage of the transistor. To mitigate the additional overhead of implementing the obfuscated circuitry, a satisfiability modulo theory (SMT) based algorithm is proposed to auto-determine the sizes of the transistors selected for obfuscation such that only a limited set of key values produce the correct circuit functionality. The proposed algorithm and the obfuscation methodology is implemented on an LC tank voltage-controlled oscillator (VCO). The operating frequency of the VCO is masked with a 24-bit encryption key applied to a 2×6 mesh structure that obfuscates the dimensions of each varactor transistor. The probability of determining the correct key is 5.96×10-8through brute force attack. The dimensions of the obfuscated transistors determined by the analog satisfiability (aSAT) algorithm result in at least a 15%, 3%, and 13% deviation in, respectively, the effective transistor dimensions, target frequency, and voltage amplitude when an incorrect key is applied to the VCO. In addition, only one key produces the desired frequency and properly sets the overall performance specifications of the VCO. The simulated results indicate that the proposed design methodology, which quickly and accurately determines the transistor sizes for obfuscation, produces the target specifications and provides protection for analog circuits against IP piracy and reverse engineering.

A novel clock generation and distribution network is proposed for multi-die architectures connected through an active silicon interposer. The proposed clock network generates and distributes a resonant clock through the active silicon interposer between dies, with each die served through resonant local clock trees. The proposed active silicon interposer rotary oscillator array (AI-ROA) serves to establish a unitary clock domain, providing constant phase and magnitude clock sources to the multiple die (i.e. multiple chiplets) in the package. Analysis is performed with multiple ARM CORTEX M0 cores per die of a homogeneous multi-die package architecture. Each M0 core of the multi-die package belongs to the unitary clock domain, designed with AI-ROA to operate at a frequency of 1 GHz. The multiple die are designed in the 28 nm technology node and the active interposer is designed in the 65 nm technology node. SPICE based simulations of post-layout models provides analysis and evaluation of the proposed architecture for performance metrics under process, voltage, and temperature variations. In particular, performance metrics are reported for 1) power consumption in comparison to PLL based architectures designed and synthesized with an industrial tool, 2) robustness against process variations, and 3) clock skew across the cores throughout the multiple die.

I. VLSI Systems: A Glance Into The Last Decades Since their inception in 1970s, VLSI systems have enabled several new technological capabilities and made them accessible to an unceasingly wider range of users, reaching a scale that has been exponentially increasing over the decades[1](seeFig. 1). Relentless integration of more complex systems has driven such remarkable evolution, as made possible by the inexorable miniaturization. As shown inFig. 1, more functionality has been crammed in a consistently smaller form factor, as exemplified by the physical volume shrinking of computers by 100 X/decade[2],[3]. At the same time, the energy per task has been decreasing at 10–100 X/decade, as shown inFig. 2, for several systems and system-on-chip subsystems[4]. This allowed packing more capabilities into the same power envelope, as generally observed in the electronic systems, even before the advent of the integrated circuit[5].

Heterogeneous Multicore Processors (HMPs) are comprised of multiple core types (small vs. big core architectures) with various performance and power characteristics which offer the flexibility to assign each thread to a core that provides the maximum energy-efficiency. Although this architecture provides more flexibility for the running application to determine the optimal run-time settings that maximize energy-efficiency, due to the interdependence of various tuning parameters such as the type of core, run-time voltage and frequency, and the number of threads, the scheduling becomes more challenging. More importantly, the impact of Power Conversion Efficiency (PCE) of the On-Chip Voltage Regulators (OCVRs) is another important parameter that makes it more challenging to schedule multithreaded applications on HMPs. In this paper, the importance of concurrent optimization and fine-tuning of the circuit and architectural parameters for energy-efficient scheduling on HMPs is addressed to harness the power of heterogeneity. In addition, the scheduling challenges for multithreaded applications are investigated for HMP architectures that account for the impact of power conversion efficiency. A highly accurate learning-based model is developed for energy-efficiency prediction to guide the scheduling decision. Using the predictive model, we further develop a PCE-aware scheduling scheme is developed for effective mapping of multithreaded applications onto an HMP. The results indicate that the proposed learning-based scheme outperforms the state of the art solution by 10% when there is no PCE gap between big and little cores. The energy-efficiency improves up to 60% when the PCE gap between big and little cores increases.

Panel Overview Known security vulnerabilities across the computing stack have caused significant concern, even requiring extensive countermeasures and system patches to address. As an example, the Meltdown and Spectre attacks, which were disclosed in January 2018, exploit architectural and circuit vulnerabilities to allow a malicious process access to secrets stored in the memory of another running program. Although software-based patches were distributed, true hardware solutions are only available through replacement.

The thermal profiles of integrated circuits (ICs) have been leveraged as a side-channel in multiple circuit and architectural scenarios. Applications range from identifying hardware Trojans to estimating the per-core power consumption of homogeneous multicore processors. Such scenarios leverage the correlation between the on-chip location of the consumed power with some target information of interest, such as correlating the extra power consumption at a specific circuit position with the presence of a hardware Trojan. While the spatial correlation between the power consumption and thermal profiles applies to all ICs, there is a fundamental difference in the context of modern SoCs. The difference stems from the presence of hardware accelerators, in which localized power consumption corresponds to the system performing the specific task that a given accelerator executes. The work described in the paper demonstrates the implications of correlating the thermal and power profiles of SoCs by presenting two working case studies that determine, at runtime, 1) the activity factor of each accelerator and 2) whether or not a system is infected by malware. This work relies on pre-processing thermal images in order to obtain a spatial profile of the estimated power density and uses a modified version of a previously developed technique that is tailored for use with accelerator-rich ICs. The resulting power estimates are fed into machine learning models that predict the core activity factor with mean average errors between 3% and 5% for the highest performing core. The statistical models used for malware detection result in an AuROC score of up to 1.0 and 0.9 when the malware offsets the activity factor of a single core by 2.5% and the 3-sigma width of the workload activity factor distribution is 2.5% and 5%, respectively.

An optimization technique is proposed to set the supply voltage of an integrated circuit for a given range of threshold voltages. The algorithm accounts for the variations in maximum operating frequency fmax, noise margins, and threshold voltage. The algorithmically determined supply and threshold voltages are compared with SPICE simulation for a 130 nm CMOS technology, where per cent error of up to 14% and 8% are observed for, respectively, the average noise margins NMavgand fmaxas compared to target circuit specifications for noise margin and frequency. The evaluated ranges of the supply and threshold voltages are, respectively, 200 mV ≤ Vdd≤ 1200 mV and 250 mV ≤ Vt≤ 700 mV. The technique is applied to both a 130 nm and 45 nm CMOS technology and results of noise margin and frequency are compared through SPICE simulation. The 45 nm technology node exhibits variation of up to 0.89× and 4.3× in, respectively, NMavgand fmaxas compared to an inverter in a 130 nm technology.

In this paper, the state space of an integrated circuit (IC) is used to increase the security of an IC against a variety of threats including intellectual property theft, IC counterfeiting, and IC overproduction. Hidden state transitions, state dependent keys, and temporal based transitions are implemented as a means to combat probing style attacks, such as the SAT attack. SPICE simulations are performed on modified state machines to characterize the overhead of implementing the three techniques in a circuit. Implementing temporal based transitions increases the area of the circuit by 68.42%, the power by 43.17%, and did not impact circuit delay. However, increasing the circuit size significantly reduces the overhead of state space encryption. For example, encrypting two registers in the s15850 ISCAS89 benchmark circuit resulted in an area overhead of 0.026%, presenting a low overhead means of securing sequential logic.

Heterogeneous architectures have emerged as a promising solution to address the dark silicon challenge by providing customized cores for each running application. To harness the power of heterogeneity, a critical challenge is simultaneously fine-tuning several parameters at the application, architecture, system, as well as circuit levels for heterogeneous architectures that improve the energy-efficiency envelope. To address this challenge, an ElasticCore platform is described where core resources along with the operating voltage and frequency settings are scaled to match the application behavior at run-time. A quantile linear regression model for power and performance prediction is used to guide the adaptation of the core resources, along with the operating voltage and frequency, to improve the energy efficiency. In addition, the dynamically scalable partitions of the ElasticCore are powered with multiple on-chip voltage regulators with high-power conversion efficiency that are able to realize fast dynamic voltage/frequency scaling. The results indicate that ElasticCore predicts application power and performance behavior with a small error at run-time across all studied benchmarks and achieves, on average close to 93% energy efficiency, as compared to an architecture with the Oracle power and performance predictor.

An energy efficient power delivery method for multi-core systems with under-provisioned on-chip voltage regulators has been proposed in literature. The power delivery network is reconfigurable at run-time to meet the varying current demands of the cores exceeding the maximum output current rating of the voltage regulators. In this paper, a real-timeworkload scheduling heuristic is developed that assigns the tasks to the cores such that the total load current consumption of the cores is always less than the total current capability of the under-provisioned on-chip voltage regulators. In addition, the energy-efficient scheduling of the tasks on to the cores ensures that the reconfiguration of the power delivery network is minimized. The heuristic includes DVFS management based on the unique constraints of the under provisioned voltage regulators. The work load scheduler is evaluated on homogeneous and heterogeneous multi-core platforms based on the Exynos 5410 big.LITTLE architecture. The proposed workload scheduler along with the run time voltage regulator clustering algorithm proposed in the literature provides a robust cross-layer power management technique for under-provisioned on-chip power delivery.

As I start my second two-year term (2017–2018) as the Editor-in-Chief (EIC) of the IEEE Transactions on Very Large Scale Integration Systems (TVLSI), I wish the TVLSI readership a very happy new year and continued professional success. It gives me great pleasure to report on the state of the journal and our performance metrics. Over the past two years, TVLSI has seen a healthy increase in the number of submissions—from 687 in 2014 to 770 in 2015, and at the time of writing of this editorial, we are at 760 submissions for 2016. We expect the number of submissions for 2016 to cross 800 before the end of the year. TVLSI, therefore, continues to be the premier archival journal for university researchers and industry practitioners in the broad area of VLSI system design.

In this paper, a dynamic on-chip power delivery system for chip multiprocessors (CMPs) is proposed, analogous to the smart grid deployed for large-scale energy distribution. The system includes underprovisioned on-chip voltage regulators (VRs) interconnected through a switch network. The peak current rating of the VRs is selected to meet only the average current demand of the cores. A real-time load-balancing algorithm is developed to reconfigure the power delivery network (PDN) by combining the output of multiple VRs when the workload demand exceeds the peak current rating of a single regulator. An operating system level task scheduling heuristic distributes the workloads on the cores such that the required reconfiguration of the PDN is minimized. Simulation results for the proposed power delivery system indicate up to a 44% reduction in the energy consumption of the CMP. In addition, the on-chip footprint of the PDN, including the on-chip VRs and the switching network, is reduced by at least 23%. The proposed cross-layer power management technique is an optimum solution for power-constrained many-core architectures implemented in advanced technology nodes.

Untrusted third-parties are found throughout the integrated circuit (IC) design flow resulting in potential threats in IC reliability and security. Threats include IC counterfeiting, intellectual property (IP) theft, IC overproduction, and the insertion of hardware Trojans. Logic encryption has emerged as a method of enhancing security against such threats, however, current implementations of logic encryption, including the XOR or look-up table (LUT) techniques, have high per-gate overheads in area, performance, and power. A novel gate level logic encryption technique with reduced per-gate overheads is described in this paper. In addition, a technique to expand the search space of a key sequence is provided, increasing the difficulty for an adversary to extract the key value. A power reduction of 41.50%, an estimated area reduction of 43.58%, and a performance increase of 34.54% is achieved when using the proposed gate level logic encryption instead of the LUT based technique for an encrypted AND gate.

A dynamic power management system for homogeneous chip multi-processors (CMP) is proposed. Each core of the CMP includes on chip DC-DC switching buck converters that are interconnected through a switch network. The peak current rating of the buck converter is selected to meet only the average current demand of the load circuit. A real-time load balancing algorithm is developed which reconfigures the power delivery network by combining the output of multiple buck converters when the workload demand exceeds the peak current rating. Simulation results for the proposed power delivery method indicate up to a 44% reduction in the energy consumption of the CMP system. In addition, the on-chip footprint of the power delivery network, including the on-chip voltage regulators and the switching network, is reduced by at least 23%.

Near-threshold computing (NTC) is a promising technique for low power applications. In this paper, novel circuit techniques for near-threshold computing are developed for improved power, performance, and robustness to noise. Two separate differential signaling based circuits are proposed which outperform CMOS and current-mode logic (CML) operating at near-threshold. The proposed circuits are described as dynamic current-mode logic (DCML) and latched DCML (LDCML). Characterization of the CMOS, CML, and the proposed DCML logic families is performed for area, power, performance and noise immunity at both the nominal and near-threshold operating voltages. At a near-threshold voltage, the DCML logic family reduces the total power by 32% while improving the performance by 82% as compared to CMOS logic. The use of DCML logic also reduces the total power consumption by 92% while improving the performance by 64% as compared to CML logic operating at near-threshold. In addition, the robustness of the proposed logic families to noise is analyzed. At near-threshold voltages, both the noise margins of LDCML is improved by more than 1.4x as compared to CMOS logic.

Integrated circuits (ICs) are used in fields such as banking, transportation, energy, health, and the military. However, the use of ICs in many applications is threatened by an increasing reliance on untrusted third-parties within the IC design flow. The result is a growing concern for IC reliability and security, with threats that include IC counterfeiting, intellectual property (IP) theft, IC overproduction, and the insertion of hardware Trojans. An area of research aimed at ensuring the reliability and security of ICs in critical applications is logic encryption. While the security of an IC is increased when using logic encryption, current methods such as the XOR or look-up table (LUT) techniques have high per-gate overheads in area, performance, and power. A reduction in the per-gate overhead permits the use of logic encryption in a wider range of applications. Novel gate level designs for logic encryption are described in this paper, resulting in reduced overhead in power, area, and performance as compared to the XOR or LUT based techniques. With the proposed gate level technique, encrypting an AND gate results in a power reduction of 43.2%, an estimated area reduction of 19.8%, and a performance increase of 46.9% in comparison to the XOR based implementation of the encrypted AND.

In this paper, a power delivery system for homogeneous chip multi-processor (CMP) systems is proposed. The power delivery system is modified at run time by clustering multiple on-chip voltage regulators (OCVR) depending on the power demand of the workload. The OCVRs are designed to deliver up to the average current requirement of the typical workloads executed on the CMP platform. When the current demand of a core cluster exceeds the average value, the output of multiple OCVRs is combined through a high-speed s witch network to provide the necessary current. Two OCVR topologies (Buck and LDO) are analyzed to characterize the impact on the characteristics of the voltage regulator as the peak load current is reduced. Simulation results for run-time OCVR clustering indicate a 36% reduction in the energy consumption of the system at an average load current with improvement in the load regulation. In addition, the area occupied by the OCVRs is reduced by at least 70%.

Heterogeneous architectures have emerged as a promising solution to enhance energy-efficiency by allowing each application to run on a core that matches resource needs more closely than a one-size-fits-all core. In this paper, an ElasticCore platform is described where core resources along with the operating voltage and frequency settings are scaled to match the application behavior at run-time. Furthermore, a linear regression model for power and performance prediction is used to guide the scaling of the core size and the operating voltage and frequency to maximize efficiency. Circuit considerations that further optimize the power efficiency of ElasticCore are also considered. Specifically, the efficiency of both off-chip and on-chip voltage regulators is analyzed for the heterogeneous architecture where the required load current changes dynamically at run-time. A distributed on-chip voltage regulator topology is proposed to accommodate the heterogeneous nature of the ElasticCore. The results indicate that ElasticCore on average achieves close to a 96% efficiency as compared to an architecture implementing the Oracle predictor where the application behavior is perfectly matched at run-time. Moreover, the proposed architecture is 30% more energy-efficient as compared to the BigLitte architecture.

In the recent years, many-core platforms have emerged to boost performance while meeting tight power constraints. Per-core Dynamic Voltage and Frequency Scaling (DVFS) maximizes energy savings and meets the performance requirements of a given workload. Given a limited number of I/O pins and the need for finer control of voltage and frequency settings per core, there is a substantial cost in using off-chip voltage regulators. Consequently, there has been increased attention on the use of on-chip voltage regulators (OCVR) in many-core systems. However, integrating OCVRs comes at a cost of reduced power conversion efficiency (PCE) and increased complexity in the power delivery network and management of the OCVRs. In this paper, the effect of PCE on the thread-to-core mapping algorithm is investigated and the importance of the PCE-aware mapping scheme to optimize energy-efficiency is highlighted. Based on the results, up to 38% more energy savings is achieved as compared to PCE-agnostic algorithms. Moreover, the impact of core clustering granularity and process variation on the total efficiency of the system is explored. When relaxing the energy constraints by just 10%, an effective mapping reduces the complexity of the power delivery system by allowing the use of a significantly smaller number of voltage regulators, as compared to per-core OCVR. The results provided in the paper indicate an important opportunity for system and circuit co-design to implement energy-efficient and complexity-effective platforms for a target workload.

A 3-D test circuit examining thermal propagation within a through-silicon via-based 3-D integrated stack has been designed, fabricated, and tested. Design insight into thermal coupling in 3-D integrated circuits (ICs) through both experiment and simulation is provided, and suggestions to mitigate thermal effects in 3-D ICs are offered. Two wafers are vertically bonded to form a 3-D stack. Intraplane and interplane thermal coupling is investigated through single-point heat generation using resistive thermal heaters and temperature monitoring through four-point resistive measurements. Thermal paths are identified and analyzed based on the metric of thermal resistance per unit length. The peak steady-state temperature due to die location within a 3-D stack is described. The reduction in peak temperature through fan-based active cooling is also reported. Thermal propagation from a heat source located on the backside of the silicon is examined with both back metal and on-chip thermal sensors. A comparison of thermal coupling between two different heat sources on the same device plane is also provided.

The on-going effort of integrating heterogeneous circuits as well as the increasing length of global interconnect are driving the semiconductor community towards 3-D integrated circuits. In this work, thermal paths within a 3-D stack are investigated using the HotSpot simulator, and the results are compared to experimental data of a fabricated two layer stack with a single back metal layer. Resistive heaters and sensors measure the heat flow in both the horizontal and vertical dimensions. The dependence of the thermal conductivity on temperature is integrated into the thermal simulation process. At high temperatures (~ 80°C), this effect is responsible for inaccuracies in the temperature and thermal resistance of up to, respectively, 20% and 28%. As confirmed by simulation, those horizontal paths that lie mostly within the silicon layer conduct more heat as compared to the vertical paths, since the thermal conductivity of silicon dioxide is ~ 200 times smaller than the thermal conductivity of silicon.

Clock distribution topologies in a three-tier 3-D integrated circuit are explored. Models of three different clock topologies are applied to determine the root to leaf delay. The models incorporate the impedance of the 3-D via between planes based on closed-form expressions of the resistance, inductance, and capacitance of a through silicon via (TSV). The resulting modeled delays are compared to experimental data. Good agreement between simulation and experimental data is achieved.

3-D integration is an important technology that addresses fundamental limitations in on-chip interconnects. Several design issues related to 3-D circuits, such as multiplane synchronization, however, need to be addressed. A comparison of three 3-D clock distribution network topologies is presented in this paper. Good agreement is shown between the modeled and experimental results of a 3-D test circuit composed of three device planes. Successful operation of the 3-D test circuit at 1.4 GHz is demonstrated. Clock skew, clock delay, signal slew, and power dissipation measurements for the different clock topologies are also provided. The measurements suggest that each topology provides certain advantages and disadvantages in terms of different performance criteria. The proper choice, consequently, of a clock distribution network is not dictated by a single design objective but rather by the overall 3-D system design requirements including availability of resources and number of bonded planes.

Continued device scaling enables microprocessors and other systems-on-chip (SoCs) to increase their performance, functionality, and hence, complexity. Simultaneously, relentless scaling, if uncompensated, degrades the performance and signal integrity of on-chip metal interconnects. These systems have therefore become increasingly communications-limited. The communications-centric nature of future high performance computing devices demands a fundamental change in intra- and inter-chip interconnect technologies.

Electrical characterization of the resistance, capacitance, and inductance of inter-plane 3-D vias is presented in this paper. Both capacitive and inductive coupling between multiple 3-D vias is described as a function of the separation distance and plane location. The effects of placing a third shield via between two signal vias is investigated as a means to limit the capacitive coupling. The location of the return path is examined to determine the best placement of a 3-D via to reduce the overall loop inductance. Based on the extracted resistance, capacitance, and inductance, the L/R time constant is shown to be much larger than the RC time constant, demonstrating that the 3-D via structure investigated in this paper is inductively limited rather than capacitively limited.