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Tien-Yuan Hsu

dblp:37/3639 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2008
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 100%

Topics — the 1 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs
FPGA power reduction		 0.112008
A generalized network flow based algorithm for power-aware FPGA memory mapping · DAC 2008

Methods — techniques the papers use, named apart from their topics

network flow · 0.1
YearPublicationVenuePosition
2008 A generalized network flow based algorithm for power-aware FPGA memory mapping
abstract
In this paper, we present a generalized network flow based algorithm for power-aware FPGA memory mapping. Our algorithm not only maps user-defined logical memories to physical embedded memory blocks under the memory resource constraint but also achieves minimum power consumption. The experimental results show that our algorithm was always able to efficiently generate optimal solutions for all test cases while an existing greedy method could do so only for about one third of the test cases.
Tien-Yuan Hsu, Ting-Chi Wang
 DAC1