Failure analysis, or forensic analysis of failed circuit elements, is an integral part of reliability assessment for the development of new materials and systems, particularly heterogeneously-integrated systems where multiple underlying failure mechanisms (modes) exist. To detect the presence of more than one failure mechanism, we usually require destructive, expensive tests (autopsies or analyses) on a number of failed units. Developing selective failure analysis strategies in the presence of limitations on time and resources is of the utmost importance. Using mixture and competing-risks models of Weibull distributions, this paper develops a probabilistic method to determine the minimum number of post-failure physical tests (analyses) required to detect the presence of more than one failure mode from the results of accelerated life tests, showing that (i) a successful detection of the presence of two distinct failure modes can be performed with 95% confidence for failure dataset sizes as small as 10 (without requiring exhaustive failure analysis on all units), and (ii) the minimum number of units to be analyzed (on average), expressed as a fraction of the sample size, decays exponentially with a power of the sample size, demonstrating the feasibility of the detection method. Our method can also handle component distributions other than Weibull. Results on three real experimental datasets are presented, along with statistical validation.

A hierarchical scheme with cells and modules is crucial for managing design complexity during a large integrated circuit design. We present a methodology for thermal aware cell-based electromigration analysis suitable for integrating electromigration reliability analysis into a conventional IC design flow. A block or cell is characterized for reliability while it is characterized for power and timing. Reusing cell characterization data significantly reduces computational load while analyzing a full-chip layout. During full-chip analysis, we compute a layout-level temperature profile from cell power dissipations using a Fast Fourier Transform based algorithm. The described full-chip reliability assessment methodology has been implemented in an interconnect reliability CAD tool. We have exercised the tool to demonstrate performance-reliability tradeoff and the significance of thermal-aware reliability analysis for true reliability aware design.

We propose a methodology using nodal analysis techniques compatible with existing computer-aided design (CAD) tools for implementing critical threshold design rules for electromigration reliability. The concept underlying critical threshold design rules is the observation that a mechanical stress-induced backflow of metal atoms is created by electromigration in interconnect lines confined by a rigid dielectric. If the steady-state balance of these two atomic fluxes is achieved before critical electromigration damage is realized, then the line can be considered to be virtually immortal with negligible reliability risk. A design rule based on this critical threshold criterion has the potential to give designers added flexibility to use currents larger than present design rules typically allow in short interconnects.