The object of algorithm design in context with a hierarchically structured memory system is a reduction of access cycles to higher memory levels by an increase of data reuse from levels closer to execution units. The object of our approach is to systematically construct an algorithm coding, starting from a weak single assignment form, so that parameters of the algorithm code (number and type of partitions, scheduling orders) can be directly mapped on parameters of the architecture (number of memory levels, size of the memories, input/output access behavior) and vice versa. Target architectures are processors with from one up to a few execution units and with a hierarchically structured memory system. The approach is based on methods derived from the realm of array synthesis and consists of a recursively defined algorithm partitioning. An approach to a quantitative determination of data reuse in recursively partitioned algorithms is given.

We consider a balanced combined application of the known LPGS- and LSGP-partitioning which we call co-partitioning. This approach allows a structural adjustment of the array design as well as a balancing of the size of the local memory and the IO-demand between the processing elements of the co-partitioned array. We determine the size of the LSGP-partitions such that there exists a sequential scheduling within the LSGP-partitions which is free of wait states. We give the proof for the existence of such a scheduling, and we give explicit formulas for the lower and upper bounds of the loops of a for-loop program which represents one of the possible sequential schedulings.