Demo Data from EDBT 2026 / reviewers in the wild / expert
James L. Turner
dblp:37/4127
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1978
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 70% Emerging computing paradigms · 23% Integrated circuit design · 7% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Emerging computing paradigms › neuromorphic computing
associative memory |
0.0 | 1 | 1978 | A Design of a Fast Cellular Associative Memory of Ordered Retrieval · IEEE Trans. Computers 1978 |
Memory systems
content-addressable memory |
0.0 | 1 | 1978 | A Design of a Fast Cellular Associative Memory of Ordered Retrieval · IEEE Trans. Computers 1978 |
Memory systems
memory architecture |
0.0 | 1 | 1978 | A Design of a Fast Cellular Associative Memory of Ordered Retrieval · IEEE Trans. Computers 1978 |
Memory systems › content-addressable memory
ordered retrieval |
0.0 | 1 | 1978 | A Design of a Fast Cellular Associative Memory of Ordered Retrieval · IEEE Trans. Computers 1978 |
Integrated circuit design
memory circuit design |
0.0 | 1 | 1978 | A Design of a Fast Cellular Associative Memory of Ordered Retrieval · IEEE Trans. Computers 1978 |
Methods — techniques the papers use, named apart from their topics
search algorithm · 0.0bit-memory logic · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1978 | A Design of a Fast Cellular Associative Memory of Ordered RetrievalabstractIn this paper, we design some simple schemes for a variety of searches, each of which may be performed in one complete memory cycle using bit-memory logic primarily. The searches we study include the basic equality search, the threshold searches (both greater than and less than searches), and most importantly, the greatest value and the least value searches. For each kind of search, we present both the algorithm suitable for our needs and the logic circuit of the memory cell required by the algorithm. Based on the basic search schemes, an algorithm for ordered retrieval is developed. A comparison for ordered retrieval schemes is then made between the proposed scheme and the previous algorithms. It is found that this algorithm outperforms all the other algorithms compared, particularly in the resolution of multiple responses. Finally, issues relating to LSI implementation, manufacturing defects, modular expansion, and extension to associative sequential memories are discussed. C. V. Ramamoorthy, James L. Turner, Benjamin W. Wah |
IEEE Trans. Computers | 2 |