We describe the implementation if an agent-based controller for an autonomous robot with cognitive abilities that reproduce homing capability in the foraging behaviour of the honeybee. The agent is based on a symbolic representation of data and information and is written in a language designed to describe fine-grained large scale parallelism, the Street language (Frost et al. 2015). The objective of this approach is to enable the direct translation of agents written in Street into embedded hardware, to achieve compact, power efficient, autonomous cognitive processing capability.

We present a 64-bit fixed-point vector multiply-accumulator (MAC) architecture capable of supporting multiple precisions. The vector MAC can perform one 64/spl times/64, two 32/spl times/32, four 16/spl times/16 or eight 8/spl times/8 bit signed/unsigned multiply-accumulates using essentially the same hardware as a scalar 64-bit MAC and with only a small increase in delay. The scalar MAC architecture is "vectorized" by inserting mode-dependent multiplexing into the partial product generation and by inserting mode-dependent kills in the carry chain of the reduction tree and the final carry-propagate adder. This is an example of "shared segmentation" in which the existing scalar structure is segmented and then shared between vector modes. The vector MAC is area efficient and can be fully pipelined which makes it suitable for high-performance processors and possibly dynamically reconfigurable processors.

While asynchronous circuits offer potential advantages over synchronous circuits, particularly in the form of low power and low noise properties, it is widely held that they are more difficult to test. The self-checking properties of semi-modular asynchronous circuits with respect to certain stuck-at faults have been known for many years, but the restrictions have been such that it has not been feasible to make use of this property to enhance testability. In this paper we demonstrate the feasibility of a technique to determine whether a proposed asynchronous circuit implementation is totally self-checking with respect to all output stuck-at-faults. This test can he incorporated into the design process to select a self-checking implementation when several alternatives are available.

In this paper we propose a workload distribution based quantized voltage level selection method called Data Dependent Level Selection (DDLS) for minimizing energy in dynamic supply voltage scaling systems. In previous works, the voltage levels have been selected by dividing the maximum normalized workload by the number of quantized voltage levels. The existing techniques place no emphasis on workload characteristics of data in selecting quantized voltage levels. Our DDLS technique is a workload distribution based technique that selects the minimum energy yielding quantized voltage levels for a given data sequence. For the 300-frame Akiyo video sequence, our DDLS analysis shows that up to 55% of energy savings can be obtained compared to the existing methods.

In this paper we propose a novel rate calculation algorithm called Quantized Rate Selection (QRS) for quantized undithered dynamic supply voltage scaling (DSVS) systems. The algorithm monitors the total buffered workload, and where possible selects a rate value equal to a quantized rate value. At quantized rate values, energy dissipation of quantized DSVS systems approaches continuous voltage level DSVS systems. Our experimental work on FMIDCT computation using nine video sequences and a 4-level quantized undithered system shows that additional energy savings of 1.4% to 18.5% can be achieved from QRS, compared to the existing averaging technique.

Support vector training requires the evaluation of a quadratic programming (QP) problem which is computationally intensive. In addition, the size of the QP is dependent on the number of training samples and may exceed the memory size. This paper presents a fast parallel implementation of the SVM on an array processor which is optimised for matrix operations. A decomposition algorithm is used to break large scale support vector problems into a fixed size block for efficient processing in the array.

Beerel (1994) showed that semimodular asynchronous circuits are totally self-checking with respect to multiple output stuck-at faults that are nonexitory and nonsubstitutional. We show that, in circuits with atomic gate implementations, it is possible to ensure that all exitory multiple output stuck-at faults will cause the circuit to halt.

We explore the potential for enhanced performance in asynchronous pipelines by the elimination of unnecessary signalling from the critical path, thus making the common case fast. An improvement of 15% over an optimal two-phase signalling approach for both static and dynamic logic control is demonstrated. We describe extensions to the approach that add functionality with no cycle time overhead.

We introduce a tabular method to perform the last two of the four phases of Martin's compilation process for asynchronous circuit design. The method is then demonstrated with three examples, illustrating that our systematic method is very straight forward, flexible, and convenient to apply, and, hence, it lends itself to automatic compilation.

Although speed independent VLSI circuit design is supported by rich theory at higher levels, it suffers from the lack of an area efficient robust transistor level implementation technique. In this paper we introduce safe cells based on which well-formed STGs can be implemented free of (delay) hazards with no unrealistic assumptions about physical gates. Although this technique still compromises chip area for the sake of preventing hazards, we show that it may achieve a significant area gain in comparison with the two-phase RS-implementation method, which is one of the few true speed independent implementation techniques that we are aware of so far. Delay hazards are then analysed in complex gate based speed independent circuits and hence theorems are developed to identify a subclass of delay hazards.

This paper presents a GaAs IEEE floating point standard single precision multiplier. A modified carry save array is used in conjunction with Booth's algorithm to reduce the partial product addition and interconnection. A special rounding technique called Trailing-1's Predictor is used to speed up the final addition and rounding. The combination of the fast arithmetic architecture and compact layout style achieves 4 ns multiplication time with 3.5 W power dissipation at 75/spl deg/C giving 14 mW/MHz. The area is 2.43 mm by 3.77 mm (excluding pads) and uses 28,000 transistors to give a density of 3056 transistors/mm/sup 2/ for 0.8-/spl mu/m GaAs technology.>