Summary form only given. Flash technology role in storage is now mainstream. Nand Flash is the nonvolatile memory behind SSD, mobile computing devices and mobile appliances (such as phones and cameras). The cost reduction pace has imposed significant challenges to the architecture of the Nand device. Also product requirements related to performance and reliability have highlighted significant problems that have to be addressed. This talk will present an overview of the Flash technology. To put the presentation in the right perspective, an introduction to various products that use flash will be given along with technical challenges that each pose. Reliability is a major requirement that Flash memories must address. This talk will prevent a discussion on factors that affect reliability, how these are addressed and expected technical challenges in the next 2-4 years.

We propose a novel design for testability technique to apply two pattern tests for path delay fault testing. Due to stringent timing requirements of deep-submicron VLSI chips, design-for-test schemes have to be tailored for detecting stuck-at as well as delay faults quickly and efficiently. Existing techniques such as enhanced scan add substantial hardware overhead, whereas techniques such as scan-shifting or functional justification make the test generation process complex and produce lower coverage for scan based designs as compared to non-scan designs. We exploit the characteristics of CMOS circuitry to enable the application of two-pattern tests. The proposed technique reduces the problem of path delay fault testing for scan based designs to that of path delay fault testing with complete accessibility to the combinational logic, and has minimal area overhead. The scheme also provides significant reduction in power during scan operation.

This paper presents a new mechanism for power analysis and reduction that exploits the hierarchical nature of circuits. A number of mechanisms have been proposed for power reduction, but they do not offer solutions in all cases. An activity-based reduction technique is presented where the clock is turned off for entire modules or sub-modules hierarchically when that portion of the circuit is not in use. Behavioral constraints are used to determine when a portion of the circuit is in use. The method shown is a top-down approach independent of the technology used during fabrication of the chip. Experimental results indicate that this method will result in a considerable reduction in power.

Logic and fault simulation are crucial steps in the design process for verifying the correctness of a circuit and generating high quality manufacturing tests. Traditionally, Intel has been relying on dedicated hardware accelerators to meet its fault grading needs. The unprecedented size and complexity of the Pentium/sup (R/)Pro microprocessor were foreseen to severely stretch the existing compute resources at Intel. Exploiting the design hierarchy and using the processing power of distributed computers were identified to be key areas which could alleviate the simulation problem. This paper describes a distributed mixed level logic and fault simulator that has been developed using an RTL simulation engine at the core, in conjunction with a gate level logic/fault simulator. The techniques and algorithm developed have been successfully applied on the Pentium/sup (R/)Pro microprocessor.

No abstract available.

A theory for error detection in linear digital state variable systems is described. With the aid of a tool called the gain matrix, it is shown that the effect of error propagation along different paths of the circuit can be analyzed. For circuits with operator fanout, it is shown that despite the fact that single faulty operators cause multiple state variables to be erroneous, no more additional check variables are required than for circuits without operator fanout. It is further shown that hardware optimization can be performed by sharing hardware functions between the original state variable system and its error detection circuitry. The analysis is performed for both single and multiple faulty operators. A scheme for error correction that performs error correction in real time is proposed. Experimental results that illustrate the practical viability of the proposed scheme are discussed.>

A greedy optimization technique for minimizing the area of linear digital systems using a combination of common subexpression elimination and modification of multiplier coefficients is proposed. Since the amount of logic required by a coefficient multiplier is dependent on the value of the coefficient, the given system is transformed, using splitting of coefficients, in such a way that the overall circuit requires a smaller area. The approach explores a much larger design space as compared to previously known techniques. The approach is the first to optimize numerically intensive digital circuits by additive decomposition of multiplier coefficients. The new synthesis scheme generates functionally equivalent but structurally different circuits with a 15 to 40% reduction in area over conventional methods, for practical circuits with DSP applications.>

A hierarchial testing approach for linear state variable digital systems based on matrix manipulation and constrained low-level test generation is reported. FEAST (functional extractor and sequential test generator) operates at the high level, where the circuit is described as an interconnection of arithmetic modules. CREST (constrained sequential test generator) operates at the low level description of the individual modules, and generates test sets satisfying constraints imposed by the high-level modules and their interconnection structure. The approach was found to perform better than automatic test generation at the gate level using existing algorithms for several large circuits.>

Delay fault testing of iterative arithmetic arrays (IAAs) is important because IAAs contain long critical paths and often determine the clock speed. A new approach, based on a weighted graph model has been developed that exploits the regularity of IAAs to select paths to be tested, and generates delay fault tests for those paths. The number of longest paths in an IAA grows exponentially with the dimension of the IAA, but the technique tests only a selected subset of longest paths, whose size is linear in the dimension of the IAA. A Monte-Carlo simulation was performed to ascertain the detection of delay faults in paths that were not explicitly tested. Promising results were obtained.>

A novel approach to fault location in linear digital data flow graphs is presented. The fault location scheme is simple and depends on the linearity property of these data flow graphs. Identification and replacement of the failed component allows operation of the circuit at the desired clock speed. It is shown how timing problems identified during speed testing of a class of circuits widely used in digital signal processing and control can be isolated to individual or sets of circuit components.>

We discuss the design and implementation of VISAGE, an object-oriented user interface framework that is part of GE's FACE Flexible Architecture Compiler Environment [1]. High-level services include a domain-independent graph editor that provides standard methods for viewing and editing hierarchical graphs, including graph layout. Editors that are customized to a specific application are built by inheritance of the domain-independent graph editor's functionality and overloading of the display, selection and editing methods. At a lower layer, presentation objects are responsible for parsing user input, displaying application output, providing mouse sensitivity and command dialogue execution. These presentation objects separate the application from its user interface, and thus promote system modularity.

Many aspects of design automation software have similar requirements for representing, manipulating, and storing design information. The recognition of these common requirements in CAD tools, allows the Flexible Architecture Compilation Environment's (FACE) Core Environment to provide a suite of high level tools for the CAD developer. The Core Environment software has been developed using object-oriented software technology, and may be readily adapted to specific applications. The focus of the core environment is to improve the productivity of CAD tool developers through better tool integration and a state-of-the-art software development environment. This Core Environment software has been used in the development of an integrated tool set covering algorithm specification, structural synthesis, and physical assembly of digital hardware systems. The focus of this paper is on the Core Environment's organization and its use in application tool development.

A scheduling and hardware sharing algorithm is presented. This algorithm is generic and can be used for synthesizing both nonpipelined and pipelined data paths. The scheduling algorithm tries to distribute operations equally among partitions to maximize hardware sharing. Multiplexer delays are explicitly considered to produce a more accurate scheduling. In hardware sharing, structural parameters such as the size of multiplexers, interconnect overhead, the size of the smallest sharable operator etc. are used to control the amount of sharing globally and produce a heuristically optimized RTL structure. The scheduling algorithm is iterated until a satisfactory structure is obtained. The algorithm also can be used for partitioning a large system into implementable pieces. The algorithm has been used successfully for synthesizing a pipelined data path from a graphics processing description that contains about 1000 components.>

A conditional resource-sharing algorithm for pipeline synthesis is presented. It allows sharing of hardware components among the mutually exclusive parts of any conditional branches appearing in a behavioral description. If done improperly, resource sharing in a conditional branch can increase its critical path delay excessively, causing performance degradation. Given area/time constraints for a pipelined design, finding an optimal conditional sharing solution is a combinatorial optimization problem. The algorithm uses heuristics with a user-defined weight that trades off area versus time; the algorithm is either manually or automatically iterated by changing the weight until a solution close to the target is obtained or is determined to be impossible to obtain. The algorithm is interactive, so designers can manually determine partial or whole sharing.>

The Flexible Architecture Compilation Environment (FACE) provides a common object-oriented representation for design information. A module-generation system built within the FACE environment that uses parameterized procedural module descriptions is discussed. These generators capture the knowledge of a designer and facilitate a high level of reuse of the modules and leaf cells. The system provides a general mechanism to parameterize design information and supports complex generators ranging from tiled structures to entire chips. This approach is applicable to many hardware architectures. Experience in the design of working VLSI chips is discussed.>

This paper describes the basic data structures and algorithms for a functional level fault simulator. The technique used is that of concurrent fault simulation. The algorithms and data structure support multi-signal value, gate and functional level device models. These algorithms and data structures also support the capability to simulate user defined faults and faults that cause timing violations. In the experimental version of the system, developed at the University of Texas, only classical stuck-at faults and faults that lead to timing discrepancies between the good and the faulty circuit were implemented. Minor additions to the data structures will allow the simulator to process non-classical faults like: (1) memory stuck-at, (2) user defined functional faults, (3) technology dependent shorted signal faults, etc. The accuracy achieved simulating a fault is consistent with the accuracy of the non-fault model.