Data-intensive functions on chip, e.g., codec, 3D graphics, pixel processing, etc. need to make best use of the increased bandwidth of multiple memories enabled by 3D die stacking via accessing multiple memories in parallel. Parallel memory accesses with originally in-order requirements necessitate reorder buffers to avoid deadlock. Reorder buffers are expensive in terms of area and power consumption. In addition, conventional reorder buffers suffer from a problem of low resource utilization. In our work, we present a novel idea, called in-network reorder buffer, to increase the utilization of reorder buffer resource. In our method, we move the reorder buffer resource and related functions from network entry/exit points to network routers. Thus, the in-network reorder buffers can be better utilized in two ways. First, they can be utilized by other packets without in-order requirements while there are no in-order packets. Second, even in-order packets can benefit from in-network reorder buffers by enjoying more shares of reorder buffers than before. Such an increase in reorder buffer utilization enables NoC performance improvement while supporting the original in-order requirements. Experimental results with an industrial strength DTV SoC example show that the presented idea improves the total execution cycle by 16.9%.

We present a high performance cache structure with a hardware prefetching mechanism that enhances exploitation of spatial and temporal locality. The proposed cache, which we call a selective-mode intelligent (SMI) cache, consists of three parts: a direct-mapped cache with a small block size, a fully associative spatial buffer with a large block size, and a hardware prefetching unit. Temporal locality is exploited by selectively moving small blocks into the direct-mapped cache after monitoring their activity in the spatial buffer for a time period. Spatial locality is enhanced by intelligently prefetching a neighboring block when a spatial buffer hit occurs. The overhead of this prefetching operation is shown to be negligible. We also show that the prefetch operation is highly accurate: Over 90 percent of all prefetches generated are for blocks that are subsequently accessed. Our results show that the system enables the cache size to be reduced by a factor of four to eight relative to a conventional direct-mapped cache while maintaining similar performance. Also, the SMI cache can reduce the miss ratio by around 20 percent and the average memory access time by 10 percent, compared with a victim-buffer cache configuration.

The zerotree wavelet coding is a very efficient image and video compression method using wavelet transform. In this paper, we introduce a grouped zerotree wavelet image coding technique with high performance that is independent on a scale of the wavelet transform. A key method that we employ is to merge the adjacent zerotrees and to transmit the merged zerotrees by one symbol. The basic idea of our algorithm can be easily applied to zerotree wavelet coders for video. Simulation results show that our algorithm outperforms previously reported zerotree wavelet coding at low bit rates and in all scales of the wavelet transform. It also preserves the advantages of the zerotree wavelet coding technique for multimedia applications.

Lowering power consumption in microprocessors, whether used in portables or not, has now become one of the most critical design concerns. On-chip cache memories tend to occupy dominant chip area in microprocessors, and it becomes increasingly important to design power-efficient cache memories. This paper describes an experimental low-power on-chip cache system designed for a 32-bit processor core called CalmRISC/sup TM-/32. A number of architectural optimizations were applied to the instruction and data caches, which significantly decrease the number of tag and data memory accesses and the amount of memory traffic to and from off-chip memory. Implemented in a 0.18 /spl mu/m CMOS technology, the presented instruction and data caches consume 90 /spl mu/A/MHz and 72 /spl mu/A/MHz at 1.8 V, respectively.

This research is to design a simple but high performance TLB (translation lookaside buffer) system with low power consumption. Thus, we propose a new TLB structure supporting two page sizes dynamically and selectively for high performance and low cost design without any operating system support. For high performance, a promotion-TLB is designed by supporting two page sizes. Also in order to attain low power consumption, a banked-TLB is constructed by dividing one fully associative TLB space into two sub fully associative TLBs. These two structures are integrated to form a banked-promotion TLB as a low power and high performance TLB structure for embedded processors. According to the results of comparison and analysis, a similar performance can be achieved by using fewer TLB entries and also energy dissipation can be reduced by around 50% compared with the fully associative TLB.

The need for a low power, high performance embedded processor has grown at a very fast pace in recent years. Embedded processors require smaller cache size for low power system-on-a-chip consideration. Decreasing cache size leads to reduced power consumption because a smaller cache has less capacitance from the bit array size as well as smaller drivers in decoder or peripheral circuitry.. Unfortunately, performance also decreases due to a lower cache hit rate when the cache size becomes smaller. Recently, to improve the miss rate on a cache, many prefetching schemes have been introduced. However, on a small cache, prefetching schemes do not perform well because projected data replace the data that a processor will need in the future. This causes cache pollution, which degrades system performance. To overcome the cache pollution on a small cache, the paper introduces a new technique called "Fixed Prefetch Block" that integrates with the prefetching scheme. To evaluate the effectiveness of our scheme, extensive stimulations on SPEC95 integer benchmarks and Mediabench benchmarks suites were performed. Results from the simulations indicate that with our proposed technique, cache pollution can be reduced on a small set associative cache.

The paper presents the low power architecture of CalmRISC, a low power 8-bit microcontroller consuming only 0.1 mW per MIPS at 3.0 V, and its efficient coprocessor interface. The architectural consideration of CalmRISC for low power consumption is presented. Some low power circuit design schemes, as well as an efficient coprocessor interface scheme in CalmRISC are proposed and discussed.

In order to reliably predict the behavior of a finite state machine (FSM) M or to generate acceptance tests for sequential designs, it is necessary to drive M to a predictable state or set of states. One possible way of accomplishing this is to have a special reset circuit to force all the latches to a specific state. However, if the circuit can be driven to a predictable state by applying an input sequence, the area required for reset circuitry can be saved. A synchronizing sequence for an FSM M is an input sequence which, when applied to any initial state of M, will drive M to a single specific state, called a reset state. An efficient and exact method for computing synchronizing sequences based on the efficient image and pre-image computation methods using binary decision diagrams is presented. The method is exact in the sense that it is a decision procedure: Given enough time and memory, the method can compute a synchronizing sequence if M has one; otherwise, the method says that M is not resettable. The theoretical heart of the proposed method is Universal Alignment, which is an analysis of the product of an FSM with itself. Algorithms and their related theorems are presented to perform the following: decide whether M has a synchronizing sequence (i.e., M is resettable), calculate a synchronizing sequence for M, calculate the set of all reset states, decide whether a specific state is a reset state. New results on the resettability of some benchmark circuits are reported.>

The binate covering problem (BCP) is the problem of finding a minimum cost assignment to variables that is a solution of a Boolean equation f=1. It is a generalization of the set covering (or unate covering) problem, where f is positive unate, and is generally given as a table with rows corresponding to the set elements and the columns corresponding to the subsets. Previous methods have considered the case when f is given as a product-of-sum formula or as a binary decision diagram (BDD). A branch-and-bound algorithm for the BCP that assumes f is expressed as the conjunction of multiple BDDs is presented. The BCP solver that has been implemented can be applied to several problems, including exact minimization of Boolean relations, for which results are presented. It has been possible to solve large, difficult problems (up to 4692 variables) which could not be solved by the product of sum based method.>

The authors present an extension to binary decision diagrams (BDDs) that exploits the information contained in the structure of the circuit to produce a compact, semicanonical representation. The extended BDDs (XBDDs) retain many of the advantages of BDDs while at the same time allowing one to deal with larger circuits. Using XBDDs, it is possible to verify circuits for which the BDDs could not be built in the same amount of space. Results of the application of XBDDs to combinational multipliers are presented.>

Algorithms are presented for finite state machine (FSM) verification and image computation which improve on the results of O. Coudert et al (1989), giving 1-4 orders of magnitude speedup. Novel features include primary input splitting-this PODEM feature enlarges the search space but shortens the search due to implications. Another new feature, identical subtree recombination, is shown to be effective for iterative networks (eg, serial multipliers). The free-variable recognition feature prevents unbalanced bipartitioning trees in tautological subspaces. Finally, reached set pruning is significant when the image contains large numbers of previously reached states.>