Abstract In the era of Large Language Models, there is still potential for improvement in current Natural Language Processing (NLP) methods in terms of verifiability and consistency. NLP classical approaches are computationally expensive due to their high-power consumption, computing power, and storage requirements. Another computationally efficient approach to NLP is categorical quantum mechanics, which combines grammatical structure and individual word meaning to deduce the sentence meaning. As both quantum theory and natural language use vector space to describe states which are more efficient on quantum hardware, QNLP models can achieve up to quadratic speedup over classical direct calculation methods. In recent years, there is significant progress in utilizing quantum features such as superposition and entanglement to represent linguistic meaning on quantum hardware. Earlier research work has already demonstrated QNLP’s potential quantum advantage in terms of speeding up search, enhancing classification tasks’ accuracy and providing an exponentially large quantum state space in which complex linguistic structures can be efficiently embedded. In this work, a QNLP model is used to determine if two sentences are related to the same topic or not. By comparing our QNLP model to a classical tensor network-based one, our model improved training accuracy by up to 45% and validation accuracy by 35%, respectively. The QNLP model convergence is also studied when varying: first, the problem size, second, parametrized quantum circuits used for model’s training, and last, the backend quantum simulator noise model. The experimental results show that strongly entangled ansatz designs result in fastest model convergence.

Abstract As the demand for cloud computing infrastructure increased, availability and reliability have become more important as they are major features in real‐time computing systems. The chances of failure in a cloud computing system increase compared to other computing systems. To achieve high reliability and availability for the cloud computing infrastructure fault tolerance is one of the most essential modules. For a cloud computing infrastructure, a proactive fault tolerance algorithm with load balancing is proposed in this paper. The proposed methodology tolerates virtual machine CPU faults to achieve maximum cloud computing infrastructure reliability and availability. CPU faults can occur during virtual machine operation. The proposed model's main objective is to track changes in CPU utilization and make a decision once a high value of CPU utilization is identified. The decision is either to migrate the defective virtual machine to another “destination host”, or to manage loads on the destination host so that the faulty virtual machine can be migrated. A load is calculated for the destination host; if the destination host is overloaded, the subroutine for load balancing is launched. Load balancing is based on the technique of choosing a virtual machine.

In cellular networks, user density and activity across network area vary from cell to another, and even at the same area over the day hours. This results in an irregular utilization of the network resources (i.e., resource blocks "RBs") across the network cells. One of the solutions to improve network utilization is the coordinated multi-point (CoMP) approach which coordinates signal transmission and reception for a user to and from multiple base stations (BSs). However, providing CoMP to all network users could waste RBs. To solve this problem, a novel clustering technique is proposed in this paper to guarantee a wise CoMP service to users based on their area density state (i.e., overloaded or under-loaded) and across different day periods. Through simulations, the proposed dynamic clustering algorithm outperforms other clustering algorithms in improving overall user throughput while maintaining the total consumed energy to acceptable levels.

This paper presents a field programmable gate array (FPGA) implementation for a competitive Hopfield neural network (CHNN) to be used in image histogram equalization (HE). This algorithm is so computationally expensive that a viable hardware implementation is appealing provided that an efficient algorithm-to-architecture mapping can be achieved. The Xilinx Virtex-E was used for the hardware realization. An efficient use of the chip is outlined in the results.

In this paper, fabric faults classification using CNeT (Behnke and Karayiannis, 1998) is studied. The basic objectives are to improve the features selection used in CNeT (Behnke and Karayiannis, 1998) classifier and compare the results with other neural network classifiers. The algorithm adopted here is composed of three stages. The first stage is a preprocessing phase where defects are detected and localized. Since every detected defect has its different shape and size, all defects are normalized to a predetermined size. In the second stage a set of features are calculated for each defect using the Haralick (1973, 1979) spatial features. The improved classification performance is achieved by employing a statistical method to select the most important features that can be used in classification. This is done by calculating a classification factor (Milligan and Cooper, 1985) for each feature vector to determine its effect in the classification process. During the third and last stage, those features are then used to train a competitive neural tree (CNeT) (Behnke and Karayiannis, 1998) designed to learn in a supervised manner the class associated with each set of features. The network can be then used to test and classify new defects. The approach is experimented with a set of images of fault free and faulty textiles and output results are compared with radial basis function classifiers.

This paper presents an FPGA implementation for the Block Truncation Coding (BTC) image compression technique. Images are divided into equal blocks. The BTC calculates the mean of each block for which a two-level quantization is performed so that a zero value is stored for the pixels with values smaller than the mean. The rest of the pixels are represented by the value one. The implementation exploits the inherent parallelism of the algorithm to provide efficient algorithm-to-architecture mapping. FPGA implementation of the BTC is composed of three modules: the input module, to receive input pixels; the quantizer module, to classify pixels to one of the two levels;= and divider circuits to obtain the two quantized values. The implementation is performed for gray and color images. The Xilinx-VirtexE BTC implementation has shown to provide about 23.4x10 6 of pixels/second processing rate which is about 3500 times faster than an Intel Pentium III-550-MHz processor.

In this paper, the problem of textile quality control is addressed. The basic objective is to classify the most important defects in woven fabrics. The algorithm adopted here is composed of three stages. The first stage is a preprocessing phase where defects are detected and localized. Since every detected defect has its different shape and size, all defects are normalized to a predetermined size. In the second stage, a set of features are calculated for each defect using the Haralick et al (1973) spatial features. During the third and last stage, those features are then used to train a competitive neural tree (CNeT) (Behnke and Karayiannis, 1998) designed to learn in a supervised manner the class associated with each set of features. The network can be then used to test and classify new defects. The approach is experimented with a set of images of fault free and defected textiles and output results are analyzed.

We develop a new software layer called the Automatic Parallel Detection Layer (APDL) for the automatic transformation from sequential to parallel code. The main interest, in this research, is the parallelism at loop level, because significant parallelism in programs almost invariably occurs in loops. The proposed APDL has five processes for code transformation: the sequential source code parser, data dependence analysis of this code, partitioning, scheduling both task and data, and generating parallel source code. Many cases have been studied to evaluate the performance of the developed layer. The performance is evaluated depending on the execution time of: the sequential code, the parallel programmer code, and the code output from APDL for the same case study. Performance results show that APDL greatly improves the execution time with respect to sequential execution time, and saves on the high cost of a parallel programmer.

The problem of textile quality control is addressed. The basic objective is to detect faults in woven fabrics. A set of statistical modules is implemented and integrated to detect the faulty textiles. The modules are divided into preprocessing modules (normalization, and median filtering) and processing modules (smoothing, and variance). The algorithms are experimented with a set of images of fault free and faulty textiles and output results are analyzed.