EDBT 2026 Demo / reviewers in the wild / expert
Babu Turumella
dblp:37/6145
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 2008
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 94% Processor architecture and microarchitecture · 6% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test › hardware verification
assertion-based verification |
0.1 | 1 | 2008 | Assertion-based verification of a 32 thread SPARCTM CMT microprocessor · DAC 2008 |
Electronic design automation › hardware verification and test
formal verification |
0.1 | 1 | 2008 | Assertion-based verification of a 32 thread SPARCTM CMT microprocessor · DAC 2008 |
Electronic design automation
hardware verification and test |
0.1 | 1 | 2008 | Assertion-based verification of a 32 thread SPARCTM CMT microprocessor · DAC 2008 |
Electronic design automation › hardware verification and test
processor verification |
0.1 | 1 | 2008 | Assertion-based verification of a 32 thread SPARCTM CMT microprocessor · DAC 2008 |
Electronic design automation › hardware verification and test › hardware verification
property checking |
0.1 | 1 | 2008 | Assertion-based verification of a 32 thread SPARCTM CMT microprocessor · DAC 2008 |
Processor architecture and microarchitecture › multithreading
chip multithreading |
0.0 | 1 | 2008 | Assertion-based verification of a 32 thread SPARCTM CMT microprocessor · DAC 2008 |
Methods — techniques the papers use, named apart from their topics
simulation-based verification · 0.1formal verification · 0.1assertion checking · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2008 | Assertion-based verification of a 32 thread SPARCTM CMT microprocessorabstractExhaustive property checking, design defect isolation and functional coverage measurement are some of the key challenges of design verification. This paper describes how an assertion based approach successfully addressed these challenges for the verification of an enterprise class chip-multi-threaded (CMT) SPARC™ microprocessor. Methodology and experiences are discussed and recommendations are made on how to incorporate this into the design verification process. Experience with using assertion checks for formal verification as well as simulation based verification is presented, which is part of over 100 person year design verification effort. Babu Turumella, Mukesh Sharma |
DAC | 1 |