Load shift keying (LSK) has been widely used in a wireless power and data transfer (WPDT) system, owing to its low cost and power consumption. It was discovered that the demodulated data can flip when the coupling coefficient ($k$) between the transmitter (TX) and receiver (RX) coils becomes less than a critical value ($k_{\mathrm {DF}}$) in a system with four basic compensation topologies (series–series, series–parallel, parallel–series, and parallel–parallel). This problem is called coupling-dependent data flipping (CDDF). Even more seriously, the transferred data cannot be recovered when$k$equals$k_{\mathrm {DF}}$. On the basis of a comprehensive circuit analysis of CDDF, a universal method applicable to all four compensation topologies was proposed. By monitoring the current through the TX coil rather than its voltage for data demodulation, CDDF can be avoided. Furthermore, a WPDT system was implemented in which the voltage information of the load resistance ($R_{\mathrm {Load}}$) was transferred to the TX side to control the source voltage for load power ($P_{\mathrm {Load}}$) regulation. Using the conventional method, CDDF along with its corresponding$k_{\mathrm {DF}}$(0.35) was verified. On the other hand, using the proposed method, the data was successfully transferred even when$k$is less than or equal to$k_{\mathrm {DF}}$. By a correct data transfer,$P_{\mathrm {Load}}$has been successfully regulated at around 1.1 W with a high system efficiency of up to 60% under the variation in$k$from 0.09 to 0.45.

Digital active gate drive enables the adjustable driving level in a switching transient for power devices. In this way, it is able to manage switching performance. However, to apply active gate drive in an inverter circuit, the sinusoidal output current turns out a critical problem for the design of driving profile because of its dependency on the load current. This paper aims to validate the feasibility of the digital active gate drive circuit using optimal patterns to adapt to sinusoidal output current of an inverter circuit. Firstly, a look-up table of optimal switching pattern under a certain load current condition was built in advance. It is noted that in the previous work, the online optimization system for finding the optimal pattern has been proposed and it is able to complete the searching of optimal switching pattern in an efficient time. Next, the output current of an inverter has been regulated to a sinusoidal waveform. Based on the output current, the corresponding optimal patterns are referred from the look-up table. Compared to conventional constant driving waveform, the power loss has been successfully reduced by 7% with the full optimal look-up table applied.

Load modulation is a common method to transfer data from the receiver (RX) side to the transmitter (TX) side in a magnetic resonance coupling wireless power transfer system. However, coupling-dependent data flipping (CDDF), that the data can be flipped depending on the coupling between TX and RX coils, is found for the first time using the conventional voltage monitoring across the TX coil. An analytic formula of the critical coupling coefficient (kC) of the coils that determines CDDF is derived. To avoid CDDF, a TX input voltage monitoring method is proposed. Both the CDDF in the conventional method and the correct data transfer without CDDF in the proposed method are demonstrated in the measurement.

A 3-level buck converter in the discontinuous conduction mode (DCM) is a key circuit for integrated voltage regulators to achieve high efficiency at a light load in the stand-by mode operation of microprocessors. In this paper, fundamental circuit characteristics including the conversion ratio and transfer function are derived for the first time, enabling the design of controllers for 3-level buck converters in the DCM. The derived transfer function is verified by time-domain small-signal-injection simulation. Similar to conventional 2-level buck converters, 3-level buck converters in the DCM have a flrst-order lag transfer function, while 3-level buck converters in the continuous conduction mode (CCM) have a second-order lag transfer function, suggesting that different controllers are required for the DCM and CCM.

A 1-Mbps, 315MHz OOK transceiver in 40-nm CMOS for body area networks is developed. Both a 38-pJ/bit carrier-frequency-free intermittent sampling receiver with -55dBm sensitivity and a 36-pJ/bit transmitter applied dual supply voltage scheme with -20dBm output power achieve the lowest energy in the published transceivers for wireless sensor networks.

A low voltage buck DC-DC converter (0.45-V input, 0.4-V output) with on-chip gate boosted (OGB) and clock frequency scaled digital PWM controller is designed in 40-nm CMOS process. The highest efficiency to date is achieved at the output power less than 40μW. In order to compensate for the die-to-die delay variations of a delay line in the proposed digital PWM controller, a linear delay trimming by a logarithmic stress voltage (LSV) scheme with good controllability is also proposed and verified in measurement.

We demonstrate ultrathin, ultraflexible, large-area pressure sensors based on an organic transistor integrated circuit. A 10-μm-thick plastic film with an organic transistor active matrix is developed that can be bent to a bending radius of less than 1 mm to create an electrical artificial skin (E-skin). The thin-film, flexible pressure-sensor matrix is implemented on a curved surface, and the spatial distribution of pressure is successfully obtained in real time.

To achieve the most energy-efficient operation, this brief presents a circuit design technique for separating the power supply voltage (VDD) of flip-flops (FFs) from that of combinational circuits, called the higher voltage FF (HVFF). Although VDDscaling can reduce the energy, the minimum operating voltage (VDDmin) of FFs prevents the operation at the optimum supply voltage that minimizes the energy, because the VDDminof FFs is higher than the optimum supply voltage. In HVFF, the VDDof combinational logic gates is reduced below the VDDminof FFs while keeping the VDDof FFs at their VDDmin. This makes it possible to minimize the energy without power and delay penalties at the nominal supply voltage (1.2 V) as well as without FF topological difications. A 16-bit integer unit with HVFF is fabricated in a 65-nm CMOS process, and measurement results show that HVFF reduces the minimum energy by 13% compared with the conventional operation, which is 1/10 times smaller than the energy at the nominal supply voltage.

In this paper, a fully integrated low voltage charge pump for thermoelectric energy harvesters is presented. The proposed dual-mode architecture achieves both the low startup voltage in a startup mode and high conversion efficiency in a normal operation mode without off-chip inductors and capacitors. In the measurement, the proposed circuit successfully converts 120-mV input to 770-mV output with 38.8% conversion efficiency.

A design methodology for sub-0.5V crystal oscillators is shown to realize an all-sub-0.5V ultra low power RF transceiver for wireless sensor networks. To reduce the minimum operating voltage (VDDmin) of the crystal oscillator, both the optimization of the gate width of the CMOS inverter in the crystal oscillator and the reduction in gate length by CMOS technology scaling are required. In accordance with the developed design methodology, a 39MHz crystal oscillator is designed and fabricated in a 40nm CMOS. The measured power consumption is 4.1μW at 0.35V and 39MHz, and the power supply voltage is the lowest among the previously reported crystal oscillators.

New measurement system for characterizing within-die delay variations of individual standard cells is presented. The proposed measurement system are able to characterize rising and falling delay variations separately by directly measuring the input and output waveforms of individual gate using an on-chip sampling oscilloscope in 65 nm 1.2V CMOS process. Seven types of standard cells are measured with 60 DUTs for each type. Good correlations of within-die delay distributions between measured and Monte Carlo simulated results are observed. The measured results of rising and falling delay are of great use to the modeling of standard cell library of deep-submicrometer process. By virtue of the proposed scheme, the relationship between the rising and falling delay variations and the active area of the standard cells is experimentally shown for the first time.

New characterizing system for within-die delay variations of individual standard cells is presented. The proposed characterizing system is able to measure rising and falling delay variations separately by directly measuring the input and output waveforms of individual gate using an on-chip sampling oscilloscope in 65nm CMOS process. 7 types of standard cells are measured with 60 DUT's for each type. Thanks to the proposed system, a relationship between the rising and falling delay variations and the active area of the standard cells is experimentally shown for the first time.

In this paper, a closed-form expression for estimating a minimum operating voltage (VDDmin) of CMOS logic gates is proposed. VDDmin is defined as the minimum supply voltage at which circuits can operate correctly. VDDmin of combinational circuits can be written as a linear function of the square-root of logarithm of the number of logic gates and its slope is proportional to the standard deviation of the within-die variation in the threshold voltage difference between PMOS and NMOS transistors. The proposed expression is verified with Monte Carlo simulations using various gate chains. The verification reveals that VDDmin of inverter chains can be estimated within 11% error. The expression is also verified with silicon measurements in a 65nm CMOS process.

Many of us in the field of ultra-low-Vddprocessors experience difficulty in assessing the sub/near threshold circuit techniques proposed by earlier papers. This paper investigates five major pitfalls which are often not appreciated by researchers when claiming that their circuits outperform others by working at a lower Vddwith a higher energy-efficiency. These pitfalls include: i) overlook the impacts of different technologies and different Vthdefinitions, ii) only emphasize energy reduction but ignore severe throughput degradation, or expect impractical pipelining depth and parallelism degree to compensate this throughput degradation, iii) unrealistically assume that memory's Vddand energy could scale as well as standard cells, iv) use the highest temperature as the worst timing corner as in the super-threshold, but in fact negative temperature becomes much more detrimental in the sub/near threshold regime, v) pursue just-in-need Vddto compensate effects of PVT, but without considering the high energy loss on DC-DC converters. Therefore, the actual energy benefit from using a sub/near threshold Vddcan be greatly overestimated. This work provides some design guidelines and silicon evidence to ultra-low-Vddsystems. The outlined pitfalls also shed light on future directions in this field.

Organic electronics is attracting a lot of attention for large-area pervasive electronics applications, because organic transistors can be fabricated using printing technologies on arbitrary substrates and this enables both high-throughput and low-cost production. In this paper, some examples of the large area electronics with the organic transistors including a wireless power transmission sheet and a communication sheet are presented. Challenges for future large area electronics are also described.

Power Gating has become one of the most widely used circuit design techniques for reducing leakage current. Its concept is very simple, but its application to standard-cell VLSI designs involves many careful considerations. The great complexity of designing a power-gated circuit originates from the side effects of inserting current switches, which have to be resolved by a combination of extra circuitry and customized tools and methodologies. In this tutorial we survey these design considerations and look at the best practice within industry and academia. Topics include output isolation and data retention, current switch design and sizing, and physical design issues such as power networks, increases in area and wirelength, and power grid analysis. Designers can benefit from this tutorial by obtaining a better understanding of implications of power gating during an early stage of VLSI designs. We also review the ways in which power gating has been improved. These include reducing the sizes of switches, cutting transition delays, applying power gating to smaller blocks of circuitry, and reducing the energy dissipated in mode transitions. Power Gating has also been combined with other circuit techniques, and these hybrids are also reviewed. Important open problems are identified as a stimulus to research.

An asynchronous threshold detector for DC-960 MHz band impulse ultra-wideband (UWB) receiver is proposed in this paper. It features a DC power-free pulse discriminator. The proposed architecture in 90 nm CMOS achieves the lowest power consumption of 0.19 mW and energy consumption of 1.9 pJ/bit at 100 Mbps in the UWB receiver.

A 3D-integrated Solid State Drive (SSD) with the boost converter can achieve both the low power and the fast write-operation at the small die area of the NAND flash memory. The performance of the boost converter, however, is critically affected by the inductor, because the output voltage of the boost converter, the rising time, and the energy consumption during the boost are determined by the inductor. Therefore, this paper proposes a design methodology of the inductor of the boost converter for the 3D SSD. By using the boost converter with the optimized inductor, the energy during write-operation of the proposed 1.8-V 3D-SSD is decreased by 68% compared with the conventional 3.3-V 3D-SSD with the charge pump.

In order to explore the feasibility of the large scale subthreshold logic circuits and to clarify the lower limit of supply voltage (VDD) for logic circuits, the dependence of minimum operating voltage (VDDmin) of CMOS logic gates on the number of stages, gate types and gate width is systematically measured with 90-nm CMOS ring oscillators (RO's). The measured average VDDmin of inverter RO's increased from 90 mV to 343 mV when the number of RO stages increased from 11 to 1Mega, which indicates the difficulty of the VDD scaling in the large scale subthreshold logic circuits. The dependence of VDDmin on the number of stages is calculated with the subthreshold current model with random threshold voltage (VTH) variations and compared with the measured results, which confirm the tendency of the measurement.

Reducing power is still the main interest in the recent integrated circuit designs. Some of the new low-power design approaches are covered in this talk. Three-dimensional stacking of chips is an effective way to reduce power by decreasing inter-chip communication energy. A low-power yet low-cost interconnection method among stacked chips is wireless communication by L-coupling and C-coupling. The recent advances in these proximity communication approaches are discussed. The other effective approach for achieving low power is to explore operations under ultra-low supply voltage. The effect of variation in the ultra-low operating supply voltage regime is discussed with measurement results. Other point of interest for power-aware systems is the source of energy. The limited access to the power source has been a limiter for the ubiquitous electronics to fly. Wireless transmission of power will offer new application scenes for ubiquitous electronics. The talk also covers an interesting yet exotic integrated circuit made of organic transistors and MEMS switches which acts as a wireless power transmission sheet and may provide a solution to last-meter problem of energy-net.

A 0.5-V sigma-delta modulator implemented in a 0.15-mum FD-SOI process with low VTHof 0.1V using analog T-switch (AT-switch) scheme to suppress subthreshold-leakage problems is presented. The scheme is compared with the conventional circuit, which are also fabricated in the same chip. The measurement result demonstrates that the sigma-delta modulator based on AT-switch realizes 6-bit resolution through reducing nonlinear leakage effects while the conventional circuit can achieve 4-bit resolution

As a candidate for the clock-gating scheme, Zigzag Super Cut-off CMOS (ZSCCMOS) has been proposed to reduce not only the switching power but also the leakage power. Due to its fast wakeup nature, the ZSCCMOS can be best suited to the clock-gating scheme. The wakeup time of the ZSCCMOS is estimated to be 12 times faster than the conventional Super Cut-off CMOS (SCCMOS) in 70-nm process technology. From the measurement of wakeup time in 0.6-/spl mu/m technology, it is observed to be eight times faster than the conventional scheme. Layout area, power, and delay overhead of the ZSCCMOS are discussed and analyzed in this paper.

This work presents a cooperative dynamic power management method and its implementation. The implementation consists of design of a real-time OS, applications including MPEG-4, and development of a supporting hardware platform with an off-the-shelf processor. We describe several factors that are important in the implementation and discuss its efficiency through experiment. The experimental results with the prototype system shows that 74% power saving is possible in multi-task multimedia environment.

Today's rising power densities have been widely cited as the foremost challenge to continued CMOS scaling. In fact, the current power crisis is reminiscent of the final days previous technologies, such as the once popular bipolar and NMOS technologies and even vacuum tubes. How CMOS technology will respond to the current power challenge to extend CMOS scaling to sub-90nm technology is an important question for designer and CAD tool developers alike. With aggressive scaling a number of new challenges have arisen, such as leakage control, heat removal and power supply distribution, that need to be addressed using new design techniques in conjunction with new CAD solutions.This panel brings together experts in circuit design and CAD tool development to discuss the current status of low-power design and provide opinions on what new EDA capabilities are most important in the power-constrained design era. For instance, how will power be distributed in a robust fashion in sub-90nm ICs, and what are the critical EDA analysis and optimization capabilities? What are the best techniques for leakage reduction, not only in standby modes, but also in the active mode? And how far will voltage scaling take us in attacking the dynamic power consumption issue? What will a power-centric design flow look like and how will it change the way we design ICs? The objective of the panel is to explore these issues and formulate a list of critical issues that need to be addressed by the EDA community to enable successful scaling of CMOS into the sub-90nm era.

A compact analytical model of variable-threshold-voltage CMOS (VTCMOS) is proposed to study the active on current, linking it with the standby off-current characteristics. Comparisons of modeled results to both numerical simulations and experimental data are made with an excellent agreement. It is clearly demonstrated using the model that speed degradation due to low supply voltage can be compensated by the VTCMOS scheme, even with smaller power. Influence of the short channel effect (SCE) on the performance of VTCMOS is investigated in terms of a new parameter, dS/d/spl gamma/, both qualitatively and quantitatively. It is found that the SCE degrades the VTCMOS performance. Issues on the optimum conditions of VTCMOS and the performance of series-connected VTCMOS circuits are also discussed.

Approaches to achieve low-power and high-speed VLSI's are described with the emphasis on techniques across multiple technology and design levels. To suppress the leakage current in a standby mode, Boosted Gate MOS (BGMOS) is effective, which is based on cooperation between technology level and circuit level. To reduce the power in an active mode, VDD-hopping and VTH-hopping are promising, which are cooperative approaches between circuit and software. Power consumed in interconnect system can be reduced by a cooperative approach between application and layout as in bus shuffling. Other low-power design approaches are also discussed.

Closed-form formulas for optimum buffer insertion where the junction capacitance is taken into account are proposed. In order to use the derived formulas, an appropriate choice of the effective linear resistance of the driving transistor is also clarified.Using the proposed formulas, the optimum interconnect delay and power comparison between bulk and SOI CMOS technology are discussed.The calculation results show that both the optimum delay and power with SOI can be reduced by 15% compared with the bulk MOSFET whose junction capacitance is assumed to be equal to the gate capacitance.

The analysis and simulation of effects induced by interconnects become increasingly important as the scale of process technologies steadily shrinks. While most analyses focus on the timing aspects of interconnects, power consumption is also important. In this paper, the power distribution analysis of interconnects is studied using a reduced-order model. The relation between power consumption and the poles and residues of a transfer function (either exact or approximated) is derived, and a simple yet accurate driver model is developed, allowing power consumption to be computed efficiently. Application of the proposed method to RC networks is demonstrated using a prototype tool.

In modern embedded systems including communication and multimedia applications, large fraction of power is consumed during memory access and data transfer. Thus, buses should be designed and optimized to consume reasonable power while delivering sufficient performance. In this paper, we address a bus ordering problem for low-power application-specific systems. A heuristic algorithm is proposed to determine the order in a way that effective lateral component of capacitance is reduced, thereby reducing the power consumed by buses. Experimental results for various examples indicate that the average power saving from 30% to 46.7% depending on capacitance components can be obtained without any circuit overhead.

Design methodology for dual-V TH scheme using commercially available tools is presented and optimization strategy for the dual-V TH scheme is discussed. In order to suppress the power consumption, it is shown that using library cells that have various combinations of V TH’s is not needed. The cell library, which contains logic gates with all high V TH transistors and all low V TH transistors, is sufficient to reduce leakage power. 0.1V is shown to be the optimum value for V TH difference between V TH,HIGH and V TH,LOW in terms of power reduction. 1.

A very compact analytical model of variable threshold voltage CMOS (VTCMOS) is proposed to study the active on-current, linking it with the stand-by off-current characteristics. Comparisons of modeled results to numerical simulations and experimental data are made with an excellent agreement. It is clearly demonstrated using the model that speed degradation due to low supply voltage can be compensated by the VTCMOS scheme with even smaller power. Influence of the short channel effect (SCE) on the performance of VTCMOS is investigated in terms of a new parameter, dS/dγ, both qualitatively and quantitatively. It is found that the SCE degrades the VTCMOS performance. Issues on the optimum conditions of VTCMOS are discussed.

Article Share on Variable threshold CMOS (VTCMOS) in series connected circuits Authors: Takashi Inukai Institute of Industrial Science, University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, Japan Institute of Industrial Science, University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, JapanView Profile , Toshiro Hiramoto Institute of Industrial Science, University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, Japan and VLSI Design and Education Center, University of Tokyo Institute of Industrial Science, University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, Japan and VLSI Design and Education Center, University of TokyoView Profile , Takayasu Sakurai Institute of Industrial Science, University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, Japan and Center for Collaborative Research, University of Tokyo Institute of Industrial Science, University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, Japan and Center for Collaborative Research, University of TokyoView Profile Authors Info & Claims ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and designAugust 2001Pages 201–206https://doi.org/10.1145/383082.383133Published:06 August 2001Publication History 10citation398DownloadsMetricsTotal Citations10Total Downloads398Last 12 Months3Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

The analysis and simulation of effects induced by VLSI interconnects become increasingly important as the scale of process technologies steadily shrinks. While most analyses focus on the timing aspects of interconnects, power consumption is also important. In this paper, the power distribution estimation of interconnects is studied using a reduced-order model. The relation between power consumption and the poles and residues of a transfer function is derived, and an appropriate driver model is developed, allowing power consumption to be computed efficiently. Application of the proposed method to RC networks is demonstrated using a prototype tool. 1.

Abstract Two compact yet high performance standard cell libraries (CyHP libraries), which contain only 11 and 20 cells respectively, are proposed. The first CyHP library leads to 5% increase in delay compared to a library containing about 400 cells. The second CyHP library suppresses delay increase up to 2%. The compact nature of these libraries not only reduces the cost and time for generation and maintenance substantially (thus enables new technologies to be adopted immediately), but also shortens synthesis time to about a half. Application results of these libraries to standard benchmarks and an industry design of about 80K gates are presented. I.

A novel hardware-software cooperative power control scheme, namely a software feedback loop, is proposed to lower power consumption of VLSI systems.The proposed runtime voltage and frequency control scheme guarantees the realtime execution of applications.It avoids interface problems and also provides "binary-code compatibility".Using a software analysis environment, the power control scheme is shown to achieve more than 90% power reduction for real-time MPEG-4 SP@L1 video encoding, taking into consideration the transition delay between voltage and frequency levels.

Abstract- Closed-form formulas are presented for optimum supply voltage (VDD) and threshold voltage (VTH) that minimize power dissipation when technology parameters and required speed are given. The formulas take into account short-channel effects and the variation of VTH and temperature. Using typical device parameters, it is shown that a simple guideline to optimize the power consumption is to set the ratio of maximum leakage power to total power about 30%. Extending the analysis, the future VLSI design trend is discussed. The optimum VDD coincides with the SIA roadmap and the optimum VTH for logic blocks at the highest temperature and at the lowest process variation corner is in the range of 0V~0.1V over generations. I.

Article Design challenges for 0.1um and beyond: embedded tutorial Share on Author: Takayasu Sakurai Center for Collaborative Research, University of Tokyo, Tokyo, Japan 106-8558 Center for Collaborative Research, University of Tokyo, Tokyo, Japan 106-8558View Profile Authors Info & Claims ASP-DAC '00: Proceedings of the 2000 Asia and South Pacific Design Automation ConferenceJanuary 2000 Pages 553–558https://doi.org/10.1145/368434.368787Online:28 January 2000Publication History 16citation121DownloadsMetricsTotal Citations16Total Downloads121Last 12 Months0Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

This paper presents a novel run-time dynamic voltage scaling scheme for low-power real-time systems. It employs software feedback control of supply voltage, which is applicable to off-the-shelf processors. It avoids interface problems from variable clock frequency. It provides efficient power reduction by fully exploiting slack time arising from workload variation. Using software analysis environment, the proposed scheme is shown to achieve 80~94% power reduction for typical real-time multimedia applications.

Power efficient design of real-time embedded systems based on programmable processors becomes more important as system functionality is increasingly realized through software. This paper presents a power optimization method for real-time embedded applications on a variable speed processor. The method combines off-line and on-line components. The off-line component determines the lowest possible maximum processor speed while guaranteeing deadlines of all tasks. The on-line component dynamically varies the processor speed or brings a processor into a power-down mode according to the status of task set in order to exploit execution time variations and idle intervals. Experimental results show that the proposed method obtains a significant power reduction across several kinds of applications.

Gate capacitance has complex voltage dependency on terminal voltages but the impact of this voltage dependency of gate capacitance on power and delay has not been fully investigated, especially, in low-voltage, low-power designs. Introducing an effective gate capacitance, CG, effit is shown that the power and delay of CMOS digital circuit can be estimated accurately. CG, effis a strong function of VTH/VDDand VTH/VDDtends to increase in low-voltage region. Hence, the effective capacitance (relative to oxide capacitance, CG, eff, is decreasing in low-voltage low-power designs. Therefore, considering CG, effin accurate power and delay) estimation becomes more important in the future.

A closed-form expression for short-circuit power dissipation of CMOS gates is presented which takes short-channel effects into consideration. The calculation results show good agreement with the SPICE simulation results over wide range of load capacitance and channel length. The change in the short-circuit power, P/sub S/, caused by the scaling in relation to the charging and discharging power, P/sub D/, is discussed and it is shown that basically power ratio, P/sub S//(P/sub D/+P/sub S/), will not change with scaling if V/sub TH//V/sub DD/ is kept constant. This paper also handles the short-circuit power of series-connected MOSFET structures which appear in NAND and other complex gates.

Simple yet useful analytical formulas for delay, slope and crosstalk noise amplitude for capacitively coupled two-, three- and infinite-line systems are derived assuming bus lines and other signal lines in deep-submicron VLSI's. The calculated results using the derived formulas are extensively compared with SPICE simulation results to demonstrate the validity of the analytical expressions. Two modes have been studied; the case where adjacent lines are driven from the opposite direction and the case where adjacent lines are driven from the same direction. These cases correspond to the typical situations in VLSI designs and include worst cases in terms of noise amplitude and delay. Delay error in approximating the distributed RC lines by N-step /spl pi/-ladder RC lumped circuit is also investigated.

A current sensing device, namely a Hall Effect MOSFET (HEMOS) is proposed. It is experimentally shown that the HEMOS enables a non-contacting, and non-disturbing current measurement, which can be used for IDDQ testing of internal circuit blocks. The HEMOS can be manufactured and integrated in a VLSI device with the conventional CMOS process. The HEMOS is also helpful in establishing the low standby current by identifying the locations of large standby power consumption (possibly a design fault) using only a few pads.

A Proximity Search Engine (PSE) which finds neighboring vectors of a specific input vector is used in various important applications such as neural network-based recognition systems, vector quantizers (VQ) and content addressable memories (CAM). It has been known, however, that the PSE is area and power hungry, since many arithmetic operations are required. In this paper, 53 /spl mu/W, 10 transistors per synapse architecture is presented which is based on current mode operations. The measurement results with 0.5 /spl mu/m CMOS process are described. Compared with previously reported neural network LSIs which need several tens of transistors per synapse including storage elements, the present scheme uses 10 MOSFETs per synapse. There has been a proposal to make use of charge-based operations in building a neural network to reduce the number of MOSFETS but it requires a double poly-Si process for capacitors of good precision. The present scheme is manufacturable with the conventional single poly CMOS process and hence is easily integratable with other CMOS processors and logic blocks. The present architecture is extensible to VQs and CAMs and can be a promising macro in system LSIs.

This paper investigates substrate noise influence on circuit performance in a variable threshold-voltage scheme (VT scheme) where threshold voltage is dynamically varied by substrate-bias control to reduce active power dissipation. It is experimentally examined that substrate-bias can be controlled stably with very few substrate-contacts. Measured tracking jitter of a delay-locked loop implemented by interconnections in an 8 mm-square gate array does not degrade even when substrate-contacts are removed except for one at every strip of p-sub and n-well: A 2 mm-square discrete cosine transform core processor with no substrate-contact except in its periphery operates at supply voltages from 1.3 V to above 3 V even though it employs small-swing differential dynamic pass-transistor logic. No performance degradation nor latchup is observed in these chips even when 100 k/spl Omega/ resistance is added to the substrate. These experimental results demonstrate noise immunity of the VT scheme, and indicate the possibility that the VT scheme can be applied to existing macro design easily.

An optimization method, called fast simulated diffusion (FSD), is proposed to solve a multiminimial optimization problem on multidimensional continuous space. The algorithm performs a greedy search and a random search alternately and can find the global minimum with a practical success rate. An efficient hill-descending method employed as the greedy search in the FSD is proposed. When the FSD is applied to a set of standard test functions, it shows an order of magnitude faster speed than the conventional simulated diffusion. Some of the optimization problems encountered in system and VLSI designs are classified into multioptimal problems. The proposed FSD is successfully applied to a MOSFET parameter extraction problem with a deep submicron MOSFET.>

A simple yet realistic MOS model called the alpha -power-law CMOS model which includes the carrier velocity saturation effect important in short-channel MOSFETs, is introduced. The model is an extension of Shockley's square law-MOS model in the saturation region. Using the model, closed-form expressions are derived for the delay, short-circuit power, and transition voltage of CMOS inverters. The resultant delay expression includes input waveform slope effects and parasitic drain/source resistance effects and can be used in simulation and/or optimization CAD tools. It is shown that the CMOS inverter delay becomes less sensitive to the input waveform slope and the short-circuit dissipation increases as MOSFETs become small.>

Application-specific integrated circuits (ASICs) with high-performance embedded memory array with suitable design route have considerable merits in terms of system speed, scalability with technology and system cost. The choice of design approach according to applications is critical. For highly memory-rich applications, one of the recently developed memory ASICs, an integrated cache memory is described. Another example suited for large-size random logic and high-density memory is a structure array approach. A recently developed 72 K track-free gate array with 1 Mb DRAM is described.>