A workflow management system is used to provide the automation and reengineering of a process. In an IC design cycle, several software tools are used to support different activities. These tools may be distributed on separate computers. An agent-based workflow management system is proposed in this paper to integrate these tools by using a scripting language. Relevant distributed software tools in agencies are managed by local agents to provide needed services. Mobile agents are used to access these services by following the proposed scripts.

As device size continues to shrink in the sub-micron regime, power supply noise is becoming a performance and reliability bottleneck in modern VLSI design. In this paper, we propose a new floorplanning methodology for fast power supply noise design convergence. By evaluating power supply noise at this early design stage, area-efficient floorplans with considering IR voltage drop and electromigration (EM) are generated. Compared to designs based on area-optimized floorplans, the proposed methodology achieves noise-satisfied designs with an average 52% less power routing resource.

In this paper, we address the problem of VLSI floorplanning with considering boundary constraints. The problem is practical and crucial in physical design since architects decide to arrange some I/O involved modules along the chip boundary to minimize both chip area and off-chip connections. By using a new representation called Generalized Polish Expression, we propose an efficient algorithm to handle the boundary constraints on non-slicing floorplans. In addition, a new fixing heuristic based on modular similarity is also presented to effectively fix the generated infeasible floorplans during the process. The experimental result is good in commonly used MCNC benchmark circuits.

In this paper, we propose a new representation of VLSI floorplan and building block problem. The representation is the generalization of Polish expression. By proposing a new relational operator, the representation can efficiently reuse some area that cannot be utilized if only having vertical and horizontal operators defined in Polish expression, and is able to present non-slicing structural floorplan. The experimental results show that the representation achieves promising area utilization in commonly used MCNC benchmark circuits.

We propose a distributed software integration architectural style (DSIAS) to provide a blueprint and reference document that would be useful to software system designers when integrating commercial off-the-shelf (COTS) products under distributed and Internet environment. DSIAS provides a framework indicating the structure topology to put lots of originally unrelated COTS products together into a COTS based system. We then successfully applied DSIAS to the design of an example, a distributed graphical parking lot management system.

We consider the problem of minimizing power consumption of a sequential circuit using low power state encoding. One of the previously published results is based on recursive matching. In general, a matched pair can be considered as a 1-cube being embedded in a hypercube. We generalize this idea of 1-cube embedding and propose a new encoding algorithm based on r-cube embedding. We then present an efficient 2-cube embedding based state encoding approach for low power design. It considers both Hamming distance and the complexity of the logic function (by estimation). Experimental results show that this approach is competitive to other existing techniques.

In this paper we examine the problem of reducing the power consumption of a technology mapped circuit under timing constraints. Consider a cell library that contains multiple implementations (cells) of the same Boolean function. We first present an exact algorithm for the problem when a complete library is given in a complete library, all implementations of each cell are present. We then propose an efficient algorithm for the problem if the provided library is not complete.

We address the problem of state encoding for synchronous finite state machines (FSM's), targeted for low power design. Most previous work in FSM state encoding has been focused on minimizing chip area and does not consider switching activity of the circuit. As a result, this does not always lead to a power efficient implementation. Especially in CMOS circuits, the switching activity is a very important factor in power dissipation. In this work, we define a function /spl lambda/ for automatic tradeoff between switching activity and area that contribute to power dissipation. /spl lambda/ is used in determining the encoding affinity between states and is observed to be related to the number of states of a FSM in our experiments. A state encoding algorithm, based on hypercube embedding, is proposed to find encodings of states such that the sum of bit toggles between each pair of states times the encoding affinity between them is minimized. Results over a wide range of MCNC benchmark examples which show the efficacy of our technique are presented.

The authors consider a Steiner tree S interconnecting a set N of terminals. The minimizing length of S can be shown to be equivalent to the traditional (NP-hard) Steiner tree problem. An exact polynomial-time algorithm for minimizing the length of S when operations on S are limited is presented. These operations are called topology preserving transformations (TPTs). Based on the notion of TPT, an exact algorithm for minimizing the total length of a single-layer layout involving a set of multi-terminal nets and a collection of obstacles is proposed. The algorithm has been used to find a minimum length single-layer layout. The algorithm was also applied to find a Steiner tree interconnecting a net N of terminals. The idea is to find a minimum spanning tree T of N. Then, generate K Steiner trees by randomly flipping edges of T to both its upper- and lower-L-shaped configurations. Then, a topology preserving transformation is applied to each Steiner tree. The best of them is selected as the final Steiner tree. On the average, 9.4% improvement over the MST length has been reported.>