In modern designs, the delay of a net can vary significantly depending on its routing. This large estimation error during the pre-routing stage can often mislead the optimization of the netlist. We extend state-of-the-art interconnect-driven physical synthesis by introducing a new paradigm (namely, persistence) that relies on guaranteed net routes for the most sensitive nets while performing circuit optimization in the pre-route stage. We implemented our proposed approach in a cutting-edge industrial physical synthesis flow; this involved the automatic identification and routing of critical nets that were likely to be mispredicted, the automatic update of their routes during the subsequent pre-routing stage optimizations, and the guaranteed retention of their routes across the routing stage. Our approach achieves significant performance improvements on a suite of real-world 65nm designs, while ensuring that the impact on their routability remains negligible. Furthermore, our experimental results scale very well with design size.

Large current in a chip can cause problems such as noise and power consumption. In this paper, a vectorless approach to analyzing a tight upper bound on the maximum instantaneous current (MIC) of a circuit is proposed. Several types of signal correlations that can cause the MIC estimation to lose accuracy are first described. Next, taking signal correlations into account, theorems to identify gates that switch mutually exclusively are proposed. In particular, the proposed algorithm can naturally consider signal correlations across sequential elements (flip-flops), whereas previous research on this topic addressed combinational circuits only. After deriving the information of mutually exclusive switching, a graph algorithm is applied to obtain an upper bound on the MIC. On average, the obtained sequential benchmark results are 179% tighter than those from the iMax algorithm and 66% tighter than those from the partial input enumeration algorithm