A new class of switching architectures for broadband packet networks, called shuffleout, is described and analyzed in the paper. Shuffleout is basically an output-queued architecture with a multistage interconnection network built out of unbuffered b/spl times/2b switching elements. Its structure is such that the number of cells that can be concurrently switched from the inlets to each output queue equals the number of stages in the interconnection network. The switching element operates the cell self-routing adopting a shortest path algorithm which, in case of conflict for interstage links, is coupled with deflection routing. The paper presents the basic shuffleout architecture, called open-loop shuffleout, in which the cells that cross the whole interconnection network without entering the addressed output queues are lost. The key target of the proposed architecture is coupling the implementation feasibility of a self-routing switch with the desirable traffic performance typical of output queueing.>

The authors describe a model for the performance evaluation of the Shuffleout asynchronous transfer mode (ATM) switch under arbitrary nonuniform traffic patterns. Shuffleout is a blocking multistage structure using shortest path routing with deflection, in which output queues are connected to all the stages. The analytical model developed computes the load on each interstage link by tracing all the paths that a packet can follow to reach the addressed switch outlet, that is, by taking into account all the deflections from its shortest path it can receive. Such a model allows the computation not only of the average load per stage but also its distribution over the different links belonging to the interstage pattern. Thus fairness in packet switching by Shuffleout is provided by the model.>