Finding the cause of yield and reliability issues has never been an easy task for the product and test engineer. The challenge continues to grow as processes add more steps and contain more complicated interactions, as designs are pushed to the limits of the process capabilities to meet their market requirements, as DPPM requirements continue to lower, and as test costs do not scale well. Test data has continued to become more critical in quickly resolving issues for fast ramps and maintenance of quality levels. However, the analysis methods are becoming more sophisticated and data intensive. This presentation will review some case studies, what was learned, and some observations.

This work proposes a wafer probe parametric test set optimization method for predicting dies which are likely to fail in the field based on known in-field or final test fails. Large volumes of wafer probe data across 5 lots and hundreds of parametric measurements are optimized to find test sets that help predict actually observed test escapes and final test failures. Simple rules are generated to explain how test limits can be tightened in wafer probe to prevent test escapes and final test fails with minimal overkill. The proposed method is evaluated on wafer probe data from a current automotive IC with near zero DPPM requirements resulting in improved test quality and reduced test cost.

This work presents a case study of wafer probe test cost reduction by multivariate parametric testset optimization for a production RF/A device. More than 1.5 million tested device samples across dozens lots and hundreds of parametric measurements are analyzed using a new automatic testset minimization system. Parametric test subsets are found that can be used to predict infrequent wafer probe failures. Multivariate test models are generated to justify removal of ineffective tests, screen failures with minimal test cost, and demonstrate that some frequently passing tests are safe drop candidates. The proposed method is evaluated using parametric test data from an RF/A IC currently in production, showing how to reduce test cost and uncover tradeoffs between test escapes and overkills during high volume wafer probe screening.

This paper studies the potential of using wafer probe tests to predict the outcome of future tests. The study is carried out using test data based on an SoC design for the automotive market. Given a set of known failing parts, there are two possible approaches to learn. First a single binary classification model can be learned to model all failing parts. We show that this approach can be effective if the failing parts are compatible in learning. Second, an individual outlier model can be learned for each failing part. We show that this approach is suitable for learning failing parts such as customer returns, where each may have a unique failing behavior. We also show that with Principal Component Analysis (PCA), a learning model can be visualized in two or three dimensional PC space, which facilitates an engineer to manually select or adjust the model.

Customer returns are defective parts that pass all functional and parametric tests, but fail in the field. To prevent customer returns, this paper analyzes wafer probe test data and tries to understand what it takes to screen them out during testing. Because these parts pass all tests, analyzing their signatures based on the original test perspective does not make sense. In this work, we search for a novel test perspective where the test signatures from parametric measurements can be used to separate the returned parts from the rest of population. Our study shows that in order to effectively screen customer returns during wafer test, a multivariate screening methodology is desired. This study is based on analyzing over 1000 parametric wafer probe tests and dies from seven lots, each lot containing one returned part. We demonstrate that analyzing customer returns from a multivariate test perspective leads to robust and conservative results.

Due to the magnitude and complexity of design and manufacturing processes, it is unrealistic to expect that models and simulations can predict all aspects of silicon behavior accurately. When unexpected behavior is observed in the post-silicon stage, one desires to identify the causes and consequently identify the fixes. This paper studies one formulation of the design-silicon mismatch problem. To analyze unexpected behavior, silicon behavior is partitioned into two classes, one class containing instances of unexpected behavior and the other with rest of the population. Classification rule learning is applied to extract rules to explain why certain class of behavior occurs. We present a rule learning algorithm that analyzes test measurement data in terms of design features to generate rules, and conduct controlled experiments to demonstrate the effectiveness of the proposed approach. Results show that the proposed learning approach can effectively uncover rules responsible for the designsilicon mismatch even when significant noises are associated with both the measurement data and the class partitioning results for capturing the unexpected behavior.

This paper proposes an online functional test selection approach based on novelty detection. Unlike other test selection methods, the idea of this paper is selecting novel functional tests to improve coverage from a large pool of available test programs before simulation. A graph based encoding scheme is developed to measure the similarity between test programs and map them into a set of feature vectors. We employ one-class SVM as the learning algorithm to detect novel tests to be simulated. While leaving the general test selection framework unchanged, the developed test program similarity measure can easily be tailored to specific applications and coverage targets based on existing simulation results. Experiments on a public domain MIPS processor design are presented to demonstrate the effectiveness of the approach.

Speed-limiting paths are critical paths that limit the performance of one or more silicon chips. This paper present a data mining methodology for analyzing speed-limiting paths extracted from AC delay test measurements. Based on data collected on 15 packaged silicon units of a four-core microprocessor design, we show that the proposed methodology can efficiently discovered actionable, design-related knowledge that would be difficult to find otherwise.

As lithography process nodes shrink to sub-wavelength levels generating acceptable layout patterns becomes a challenging problem. Traditionally, complex convolution based lithography simulations are used to estimate areas of high variability. These methods are slow and infeasible for large scale full chip analysis. This work proposes a solution to this problem by using machine learning techniques to identify layout areas that are more prone to variability. A novel target layout representation is proposed, and the latest support vector machine (SVM) algorithms are used to detect variability within standard cells and between cells in a simulated full chip layout.

This work proposes a methodology to minimize the application cost of outlier analysis when applied to delay testing in the presence of systematic variability. Support vector machine (SVM) outlier analysis algorithms and traditional entropy measures are used to detect delay defects by choosing a minimum number of suitable test clocks. Monte Carlo simulations generate realistic test data while information content measurements guide test clock selection. Exhaustive simulation found trade-offs between reducing the number of clocks, patterns, and chip samples. Substantial cost reduction was obtained with proper clock selection, while minimizing both test patterns and circuit samples required for effective outlier analysis.

This work provides a survey study of several outlier analysis techniques and compares their effectiveness in the context of delay testing. Three different approaches are studied, an Euclidean-distance based algorithm, random forest, and one-class support vector machine (SVM), from which more advanced methods are derived and analyzed. We conclude that one-class SVM using a polynomial kernel is most effective for detecting delay defects, while keeping overkills minimized. The best models were successfully validated and a feasible approach to delay testing using one-class SVM is proposed.