There is an urgent need for ''T-shaped'' software developers with breadth in Quantum Computing (QC) and depth in Computer Science and Software Engineering, who can build and work with the quantum-powered applications of the near future. This paper reports on our experiences implementing the Quantum-Aware (Q-Aware) track, an adaptable and lightweight curricular framework that can be integrated into existing curricula for the preparation of quantum-aware graduates. Our focus here is a study conducted on the integration of Q-Aware into Data Structures and Discrete Structures courses during Fall 2025. One goal of this study was to investigate the effectiveness of Q-Aware in helping students achieve the level of knowledge and skills for quantum awareness. In addition to a high level of enthusiasm of students for participation in Q-Aware, we observed a substantial increase in confidence of students when it comes to understanding concepts such as qubit, quantum state, superposition and quantum measurement. A second goal was to assess the effectiveness of QC training for the instructors teaching these courses. Student feedback was positive overall about the effectiveness of lectures, motivating students, effective use of time, and handling students' questions.

Mower is a micro-architecture technique which targets the branch misprediction penalty in superscalar processors. It speeds-up the misprediction recovery process by dynamically evicting stale instructions and correcting the Register Alias Table (RAT) using explicit control dependency tracking. Tracking control dependencies is accomplished by using simple bit matrices. This low-overhead technique allows overlapping of the recovery process with instruction fetching, renaming and scheduling from the correct path. Our evaluation of the mechanism indicates that it yields performance very close to ideal recovery and provides up to 5% speed-up and 2% reduction in power consumption compared to a recovery mechanism using a reorder buffer and a walker. The simplicity of the mechanism should permit easy implementation of Mower in an actual processor.

LaZy Superscalar is a processor architecture which delays the execution of fetched instructions until their results are needed by other instructions. This approach eliminates dead instructions and provides the necessary means to fuse dependent instructions across multiple control dependencies by explicitly tracking control and data dependencies through a matrix based scheduler. We present this novel redesign of scheduling, recovery and commit mechanisms and evaluate the performance of the proposed architecture. Our simulations using Spec 2006 benchmark suite indicate that LaZy Superscalar can achieve significant speed-ups while providing respectable power savings compared to a conventional superscalar processor.